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AEW2015AEW2015
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Build for arty demo
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‎.gitignore

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FIG/digilent_arty/dut/vivado_project/
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*.bin
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*.bit
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*.edf

‎.gitmodules

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[submodule "FIG/digilent_arty/dut/soft_riscv"]
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path = FIG/digilent_arty/dut/sw/soft_riscv
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url = https://github.com/AEW2015/soft_riscv.git
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[submodule "FIG/digilent_arty/dut/hdl/kronos"]
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path = FIG/digilent_arty/dut/kronos
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url = https://github.com/SonalPinto/kronos.git
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[submodule "FIG/digilent_arty/dut/hdl/picorv32"]
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path = FIG/digilent_arty/dut/picorv32
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url = https://github.com/YosysHQ/picorv32.git

‎FIG/digilent_arty/dut/build_dut.tcl

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#*****************************************************************************************
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# Vivado (TM) v2021.2.1 (64-bit)
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#
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# build_dut.tcl: Tcl script for re-creating project 'arty_kornos'
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#
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# Generated by Vivado on Tue Nov 01 11:12:33 -0600 2022
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# IP Build 3405791 on Sun Dec 19 15:54:35 MST 2021
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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# when this script was generated. In order to re-create the project, please source this
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# file in the Vivado Tcl Shell.
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#
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# * Note that the runs in the created project will be configured the same way as the
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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#
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#*****************************************************************************************
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# Check file required for this script exists
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set origin_dir "."
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# Use origin directory path location variable, if specified in the tcl shell
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if { [info exists ::origin_dir_loc] } {
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set origin_dir $::origin_dir_loc
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}
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# Set the project name
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set _xil_proj_name_ "vivado_project"
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# Use project name variable, if specified in the tcl shell
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if { [info exists ::user_project_name] } {
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set _xil_proj_name_ $::user_project_name
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}
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variable script_file
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set script_file "build_dut.tcl"
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# Create project
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create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35ticsg324-1L
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# Set the directory path for the new project
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set proj_dir [get_property directory [current_project]]
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# Set project properties
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set obj [current_project]
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set_property -name "board_part" -value "digilentinc.com:arty-a7-35:part0:1.0" -objects $obj
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set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
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set_property -name "enable_vhdl_2008" -value "1" -objects $obj
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set_property -name "ip_cache_permissions" -value "read write" -objects $obj
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set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
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set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
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set_property -name "platform.board_id" -value "arty" -objects $obj
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set_property -name "revised_directory_structure" -value "1" -objects $obj
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set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
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set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
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set_property -name "simulator_language" -value "Mixed" -objects $obj
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set_property -name "target_language" -value "VHDL" -objects $obj
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set_property -name "webtalk.activehdl_export_sim" -value "18" -objects $obj
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set_property -name "webtalk.ies_export_sim" -value "10" -objects $obj
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set_property -name "webtalk.modelsim_export_sim" -value "18" -objects $obj
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set_property -name "webtalk.questa_export_sim" -value "18" -objects $obj
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set_property -name "webtalk.riviera_export_sim" -value "18" -objects $obj
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set_property -name "webtalk.vcs_export_sim" -value "18" -objects $obj
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set_property -name "webtalk.xcelium_export_sim" -value "5" -objects $obj
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set_property -name "webtalk.xsim_export_sim" -value "18" -objects $obj
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set_property -name "webtalk.xsim_launch_sim" -value "20" -objects $obj
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set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Add local files from the original project (-no_copy_sources specified)
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set files [list \
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[file normalize "${origin_dir}/hdl/kronos_v.vhd" ]\
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[file normalize "${origin_dir}/picorv32/picorv32.v" ]\
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]
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set added_files [add_files -fileset sources_1 $files]
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# Set 'sources_1' fileset file properties for local files
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set file "hdl/kronos_v.vhd"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "VHDL" -objects $file_obj
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set_property -name "is_enabled" -value "1" -objects $file_obj
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set_property -name "is_global_include" -value "0" -objects $file_obj
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set_property -name "library" -value "xil_defaultlib" -objects $file_obj
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set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
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set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
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set_property -name "used_in_simulation" -value "1" -objects $file_obj
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set_property -name "used_in_synthesis" -value "1" -objects $file_obj
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set file "picorv32/picorv32.v"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "Verilog" -objects $file_obj
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set_property -name "is_enabled" -value "1" -objects $file_obj
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set_property -name "is_global_include" -value "0" -objects $file_obj
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set_property -name "library" -value "xil_defaultlib" -objects $file_obj
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set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
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set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
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set_property -name "used_in_simulation" -value "1" -objects $file_obj
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set_property -name "used_in_synthesis" -value "1" -objects $file_obj
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import_files -norecurse ${origin_dir}/ip/clk_wiz_0.xci
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set_property ip_repo_paths $origin_dir/ip/ip_repo [current_project]
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update_ip_catalog
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source ./tcl/kron_bd.tcl
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update_compile_order -fileset sources_1
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# Set 'sources_1' fileset properties
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set obj [get_filesets sources_1]
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set_property -name "design_mode" -value "RTL" -objects $obj
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set_property -name "edif_extra_search_paths" -value "" -objects $obj
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set_property -name "elab_link_dcps" -value "1" -objects $obj
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set_property -name "elab_load_timing_constraints" -value "1" -objects $obj
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set_property -name "generic" -value "" -objects $obj
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set_property -name "include_dirs" -value "" -objects $obj
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set_property -name "lib_map_file" -value "" -objects $obj
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set_property -name "loop_count" -value "1000" -objects $obj
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set_property -name "name" -value "sources_1" -objects $obj
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set_property -name "top" -value "tma_wrap" -objects $obj
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set_property -name "top_auto_set" -value "0" -objects $obj
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set_property -name "verilog_define" -value "" -objects $obj
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set_property -name "verilog_uppercase" -value "0" -objects $obj
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set_property -name "verilog_version" -value "verilog_2001" -objects $obj
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set_property -name "vhdl_version" -value "vhdl_2k" -objects $obj
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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create_fileset -constrset constrs_1
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}
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add_files $origin_dir/kronos/rtl
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add_files $origin_dir/hdl
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add_files -fileset constrs_1 $origin_dir/xdc/arty_a7.xdc
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set_property top design_1_wrapper [current_fileset]
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update_compile_order -fileset sources_1
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update_compile_order -fileset sources_1
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puts "INFO: Project created:${_xil_proj_name_}"
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set_property generic "NUM_PROS=1 USE_BSCAN=false" [current_fileset]
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set_property strategy Flow_AlternateRoutability [get_runs synth_1]
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set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
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set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
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set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
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launch_runs impl_1 -to_step write_bitstream -jobs 6
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wait_on_run impl_1
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open_run impl_1
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write_edif $origin_dir/outputs/kronos.edf
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write_bitstream -bin_file $origin_dir/outputs/kronos.bit
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close_project

‎FIG/digilent_arty/dut/hdl/FIFO.vhd

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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 03/03/2017 11:08:09 AM
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-- Design Name:
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-- Module Name: FIFO - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity FIFO is
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Generic (
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constant DATA_WIDTH : positive := 8;
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constant FIFO_DEPTH : positive := 156);
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Port (
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CLK : in STD_LOGIC;
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RST_N : in STD_LOGIC;
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WriteEn : in STD_LOGIC;
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DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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ReadEn : in STD_LOGIC;
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DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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Empty : out STD_LOGIC;
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Full : out STD_LOGIC
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);
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end FIFO;
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architecture Behavioral of FIFO is
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begin
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-- Memory Pointer Process
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fifo_proc : process (CLK)
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type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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variable Memory : FIFO_Memory;
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variable Head : natural range 0 to FIFO_DEPTH - 1;
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variable Tail : natural range 0 to FIFO_DEPTH - 1;
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variable Looped : boolean;
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begin
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if rising_edge(CLK) then
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if RST_N = '0' then
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Head := 0;
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Tail := 0;
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Looped := false;
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Full <= '0';
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Empty <= '1';
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else
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if (ReadEn = '1') then
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if ((Looped = true) or (Head /= Tail)) then
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-- Update data output
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DataOut <= Memory(Tail);
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-- Update Tail pointer as needed
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if (Tail = FIFO_DEPTH - 1) then
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Tail := 0;
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Looped := false;
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else
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Tail := Tail + 1;
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end if;
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end if;
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end if;
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if (WriteEn = '1') then
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if ((Looped = false) or (Head /= Tail)) then
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-- Write Data to Memory
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Memory(Head) := DataIn;
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-- Increment Head pointer as needed
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if (Head = FIFO_DEPTH - 1) then
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Head := 0;
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Looped := true;
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else
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Head := Head + 1;
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end if;
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end if;
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end if;
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-- Update Empty and Full flags
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if (Head = Tail) then
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if Looped then
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Full <= '1';
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else
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Empty <= '1';
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end if;
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else
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Empty <= '0';
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Full <= '0';
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end if;
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end if;
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end if;
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end process;
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end Behavioral;

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