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drm: Add support for Amlogic Meson Graphic Controller
The Amlogic Meson Display controller is composed of several components : DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| | vd1 _______ _____________ _________________ | | D |-------| |----| | | | | HDMI PLL | D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | R |-------| |----| Processing | | | | | | osd2 | | | |---| Enci ----------|----|-----VDAC------| R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | Encl ----------|----|---------------| M |-------|______|----|____________| |________________| | | ___|__________________________________________________________|_______________| VIU: Video Input Unit --------------------- The Video Input Unit is in charge of the pixel scanout from the DDR memory. It fetches the frames addresses, stride and parameters from the "Canvas" memory. This part is also in charge of the CSC (Colorspace Conversion). It can handle 2 OSD Planes and 2 Video Planes. VPP: Video Post Processing -------------------------- The Video Post Processing is in charge of the scaling and blending of the various planes into a single pixel stream. There is a special "pre-blending" used by the video planes with a dedicated scaler and a "post-blending" to merge with the OSD Planes. The OSD planes also have a dedicated scaler for one of the OSD. VENC: Video Encoders -------------------- The VENC is composed of the multiple pixel encoders : - ENCI : Interlace Video encoder for CVBS and Interlace HDMI - ENCP : Progressive Video Encoder for HDMI - ENCL : LCD LVDS Encoder The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock tree and provides the scanout clock to the VPP and VIU. The ENCI is connected to a single VDAC for Composite Output. The ENCI and ENCP are connected to an on-chip HDMI Transceiver. This driver is a DRM/KMS driver using the following DRM components : - GEM-CMA - PRIME-CMA - Atomic Modesetting - FBDev-CMA For the following SoCs : - GXBB Family (S905) - GXL Family (S905X, S905D) - GXM Family (S912) The current driver only supports the CVBS PAL/NTSC output modes, but the CRTC/Planes management should support bigger modes. But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in a second time. The Device Tree bindings makes use of the endpoints video interface definitions to connect to the optional CVBS and in the future the HDMI Connector nodes. HDMI Support is planned for a next release. Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
1 parent bc33b0c commit bbbe775

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+3876
-0
lines changed

‎drivers/gpu/drm/Kconfig

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@@ -223,6 +223,8 @@ source "drivers/gpu/drm/hisilicon/Kconfig"
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source "drivers/gpu/drm/mediatek/Kconfig"
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source "drivers/gpu/drm/meson/Kconfig"
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# Keep legacy drivers last
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menuconfig DRM_LEGACY

‎drivers/gpu/drm/Makefile

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@@ -79,6 +79,7 @@ obj-$(CONFIG_DRM_TEGRA) += tegra/
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obj-$(CONFIG_DRM_STI) += sti/
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obj-$(CONFIG_DRM_IMX) += imx/
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obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
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obj-$(CONFIG_DRM_MESON) += meson/
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obj-y += i2c/
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obj-y += panel/
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obj-y += bridge/

‎drivers/gpu/drm/meson/Kconfig

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config DRM_MESON
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tristate "DRM Support for Amlogic Meson Display Controller"
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depends on DRM && OF && (ARM || ARM64)
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depends on ARCH_MESON || COMPILE_TEST
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select DRM_KMS_HELPER
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select DRM_KMS_CMA_HELPER
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select DRM_GEM_CMA_HELPER
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select VIDEOMODE_HELPERS
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select REGMAP_MMIO

‎drivers/gpu/drm/meson/Makefile

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meson-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o
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meson-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_canvas.o
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obj-$(CONFIG_DRM_MESON) += meson.o

‎drivers/gpu/drm/meson/meson_canvas.c

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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <[email protected]>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include "meson_drv.h"
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#include "meson_canvas.h"
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#include "meson_registers.h"
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/*
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* CANVAS is a memory zone where physical memory frames information
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* are stored for the VIU to scanout.
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*/
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/* DMC Registers */
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#define DMC_CAV_LUT_DATAL 0x48 /* 0x12 offset in data sheet */
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#define CANVAS_WIDTH_LBIT 29
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#define CANVAS_WIDTH_LWID 3
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#define DMC_CAV_LUT_DATAH 0x4c /* 0x13 offset in data sheet */
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#define CANVAS_WIDTH_HBIT 0
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#define CANVAS_HEIGHT_BIT 9
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#define CANVAS_BLKMODE_BIT 24
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#define DMC_CAV_LUT_ADDR 0x50 /* 0x14 offset in data sheet */
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#define CANVAS_LUT_WR_EN (0x2 << 8)
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#define CANVAS_LUT_RD_EN (0x1 << 8)
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void meson_canvas_setup(struct meson_drm *priv,
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uint32_t canvas_index, uint32_t addr,
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uint32_t stride, uint32_t height,
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unsigned int wrap,
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unsigned int blkmode)
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{
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unsigned int val;
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regmap_write(priv->dmc, DMC_CAV_LUT_DATAL,
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(((addr + 7) >> 3)) |
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(((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
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regmap_write(priv->dmc, DMC_CAV_LUT_DATAH,
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((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<
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CANVAS_WIDTH_HBIT) |
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(height << CANVAS_HEIGHT_BIT) |
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(wrap << 22) |
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(blkmode << CANVAS_BLKMODE_BIT));
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regmap_write(priv->dmc, DMC_CAV_LUT_ADDR,
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CANVAS_LUT_WR_EN | canvas_index);
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/* Force a read-back to make sure everything is flushed. */
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regmap_read(priv->dmc, DMC_CAV_LUT_DATAH, &val);
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}

‎drivers/gpu/drm/meson/meson_canvas.h

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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <[email protected]>
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* Canvas LUT Memory */
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#ifndef __MESON_CANVAS_H
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#define __MESON_CANVAS_H
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#define MESON_CANVAS_ID_OSD1 0x4e
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/* Canvas configuration. */
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#define MESON_CANVAS_WRAP_NONE 0x00
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#define MESON_CANVAS_WRAP_X 0x01
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#define MESON_CANVAS_WRAP_Y 0x02
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#define MESON_CANVAS_BLKMODE_LINEAR 0x00
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#define MESON_CANVAS_BLKMODE_32x32 0x01
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#define MESON_CANVAS_BLKMODE_64x64 0x02
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void meson_canvas_setup(struct meson_drm *priv,
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uint32_t canvas_index, uint32_t addr,
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uint32_t stride, uint32_t height,
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unsigned int wrap,
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unsigned int blkmode);
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#endif /* __MESON_CANVAS_H */

‎drivers/gpu/drm/meson/meson_crtc.c

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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <[email protected]>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
13+
* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Written by:
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* Jasper St. Pierre <[email protected]>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_flip_work.h>
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#include <drm/drm_crtc_helper.h>
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#include "meson_crtc.h"
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#include "meson_plane.h"
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#include "meson_vpp.h"
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#include "meson_viu.h"
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#include "meson_registers.h"
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/* CRTC definition */
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struct meson_crtc {
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struct drm_crtc base;
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struct drm_pending_vblank_event *event;
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struct meson_drm *priv;
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};
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#define to_meson_crtc(x) container_of(x, struct meson_crtc, base)
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/* CRTC */
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static const struct drm_crtc_funcs meson_crtc_funcs = {
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.destroy = drm_crtc_cleanup,
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.page_flip = drm_atomic_helper_page_flip,
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.reset = drm_atomic_helper_crtc_reset,
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.set_config = drm_atomic_helper_set_config,
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};
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static void meson_crtc_enable(struct drm_crtc *crtc)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct drm_plane *plane = meson_crtc->priv->primary_plane;
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struct meson_drm *priv = meson_crtc->priv;
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/* Enable VPP Postblend */
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writel(plane->state->crtc_w,
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priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
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writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
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priv->io_base + _REG(VPP_MISC));
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priv->viu.osd1_enabled = true;
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}
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static void meson_crtc_disable(struct drm_crtc *crtc)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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priv->viu.osd1_enabled = false;
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/* Disable VPP Postblend */
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writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
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priv->io_base + _REG(VPP_MISC));
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if (crtc->state->event && !crtc->state->active) {
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spin_lock_irq(&crtc->dev->event_lock);
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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spin_unlock_irq(&crtc->dev->event_lock);
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crtc->state->event = NULL;
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}
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}
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static void meson_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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unsigned long flags;
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if (crtc->state->event) {
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WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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meson_crtc->event = crtc->state->event;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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crtc->state->event = NULL;
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}
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}
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static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
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struct meson_drm *priv = meson_crtc->priv;
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if (priv->viu.osd1_enabled)
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priv->viu.osd1_commit = true;
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}
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static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
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.enable = meson_crtc_enable,
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.disable = meson_crtc_disable,
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.atomic_begin = meson_crtc_atomic_begin,
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.atomic_flush = meson_crtc_atomic_flush,
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};
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void meson_crtc_irq(struct meson_drm *priv)
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{
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struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc);
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unsigned long flags;
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/* Update the OSD registers */
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if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
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writel_relaxed(priv->viu.osd1_ctrl_stat,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
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writel_relaxed(priv->viu.osd1_blk0_cfg[0],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
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writel_relaxed(priv->viu.osd1_blk0_cfg[1],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
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writel_relaxed(priv->viu.osd1_blk0_cfg[2],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
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writel_relaxed(priv->viu.osd1_blk0_cfg[3],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
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writel_relaxed(priv->viu.osd1_blk0_cfg[4],
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priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
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/* If output is interlace, make use of the Scaler */
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if (priv->viu.osd1_interlace) {
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struct drm_plane *plane = priv->primary_plane;
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struct drm_plane_state *state = plane->state;
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struct drm_rect dest = {
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.x1 = state->crtc_x,
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.y1 = state->crtc_y,
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.x2 = state->crtc_x + state->crtc_w,
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.y2 = state->crtc_y + state->crtc_h,
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};
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meson_vpp_setup_interlace_vscaler_osd1(priv, &dest);
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} else
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meson_vpp_disable_interlace_vscaler_osd1(priv);
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/* Enable OSD1 */
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writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
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priv->io_base + _REG(VPP_MISC));
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priv->viu.osd1_commit = false;
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}
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drm_crtc_handle_vblank(priv->crtc);
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spin_lock_irqsave(&priv->drm->event_lock, flags);
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if (meson_crtc->event) {
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drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event);
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drm_crtc_vblank_put(priv->crtc);
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meson_crtc->event = NULL;
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}
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spin_unlock_irqrestore(&priv->drm->event_lock, flags);
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}
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int meson_crtc_create(struct meson_drm *priv)
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{
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struct meson_crtc *meson_crtc;
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struct drm_crtc *crtc;
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int ret;
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meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
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GFP_KERNEL);
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if (!meson_crtc)
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return -ENOMEM;
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meson_crtc->priv = priv;
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crtc = &meson_crtc->base;
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ret = drm_crtc_init_with_planes(priv->drm, crtc,
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priv->primary_plane, NULL,
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&meson_crtc_funcs, "meson_crtc");
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if (ret) {
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dev_err(priv->drm->dev, "Failed to init CRTC\n");
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return ret;
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}
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drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs);
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priv->crtc = crtc;
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return 0;
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}

‎drivers/gpu/drm/meson/meson_crtc.h

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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <[email protected]>
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
7+
* modify it under the terms of the GNU General Public License as
8+
* published by the Free Software Foundation; either version 2 of the
9+
* License, or (at your option) any later version.
10+
*
11+
* This program is distributed in the hope that it will be useful, but
12+
* WITHOUT ANY WARRANTY; without even the implied warranty of
13+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14+
* General Public License for more details.
15+
*
16+
* You should have received a copy of the GNU General Public License
17+
* along with this program; if not, see <http://www.gnu.org/licenses/>.
18+
*
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* Written by:
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* Jasper St. Pierre <[email protected]>
21+
*/
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#ifndef __MESON_CRTC_H
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#define __MESON_CRTC_H
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#include "meson_drv.h"
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int meson_crtc_create(struct meson_drm *priv);
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void meson_crtc_irq(struct meson_drm *priv);
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#endif /* __MESON_CRTC_H */

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