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Update dag_circuit.rs
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crates/circuit/src/dag_circuit.rs

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Original file line numberDiff line numberDiff line change
@@ -5688,13 +5688,8 @@ impl DAGCircuit {
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} else if let Ok(clbit) = wire.extract::<ShareableClbit>() {
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NodeType::ClbitOut(self.clbits.find(&clbit).unwrap())
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} else {
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<<<<<<< HEAD
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let var = VarAsKey::new(wire);
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NodeType::VarIn(self.vars.find(&var).unwrap())
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=======
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let var = PyObjectAsKey::new(wire);
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NodeType::VarOut(self.vars.find(&var).unwrap())
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>>>>>>> ddd04013f (Fix deepcopy/pickle of `DAGCircuit` variable IO nodes (#14041))
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}
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} else if let Ok(op_node) = b.downcast::<DAGOpNode>() {
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let op_node = op_node.borrow();

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