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[ihp][WIP] ol2/tt_top: HACKS for iHP-SG13G2
Signed-off-by: Sylvain Munaut <[email protected]>
1 parent 33cba2c commit c5d978b

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8 files changed

+570
-118
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8 files changed

+570
-118
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‎ol2/tt_top/build.py

+54-25
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
from openlane.flows.misc import OpenInKLayout
2020
from openlane.flows.sequential import SequentialFlow
2121
from openlane.steps.odb import OdbpyStep
22+
from openlane.steps.openroad import OpenROADStep
2223
from openlane.steps import (
2324
Step,
2425
Yosys,
@@ -35,6 +36,7 @@
3536
import tt
3637

3738

39+
@Step.factory.register()
3840
class CustomPower(OdbpyStep):
3941

4042
id = "TT.Top.CustomPower"
@@ -47,6 +49,7 @@ def get_script_path(self):
4749
)
4850

4951

52+
@Step.factory.register()
5053
class CustomRoute(OdbpyStep):
5154

5255
id = "TT.Top.CustomRoute"
@@ -59,6 +62,19 @@ def get_script_path(self):
5962
)
6063

6164

65+
@Step.factory.register()
66+
class PadRing(OpenROADStep):
67+
68+
id = "TT.Top.PadRing"
69+
name = "Creates Pad Ring"
70+
71+
def get_script_path(self):
72+
return os.path.join(
73+
os.path.dirname(__file__),
74+
"padring.tcl"
75+
)
76+
77+
6278
class TopFlow(SequentialFlow):
6379

6480
Steps: List[Type[Step]] = [
@@ -67,9 +83,9 @@ class TopFlow(SequentialFlow):
6783
Checker.YosysUnmappedCells,
6884
Checker.YosysSynthChecks,
6985
OpenROAD.Floorplan,
70-
Odb.ApplyDEFTemplate,
71-
Odb.ManualMacroPlacement,
7286
CustomPower,
87+
PadRing,
88+
Odb.ManualMacroPlacement,
7389
OpenROAD.GeneratePDN,
7490
OpenROAD.GlobalPlacement,
7591
OpenROAD.DetailedPlacement,
@@ -82,18 +98,18 @@ class TopFlow(SequentialFlow):
8298
Odb.ReportWireLength,
8399
Checker.WireLength,
84100
OpenROAD.RCX,
85-
OpenROAD.STAPostPNR,
86-
OpenROAD.IRDropReport,
87-
Magic.StreamOut,
101+
# OpenROAD.STAPostPNR,
102+
# OpenROAD.IRDropReport,
103+
# Magic.StreamOut,
88104
KLayout.StreamOut,
89-
KLayout.XOR,
90-
Checker.XOR,
91-
Magic.DRC,
92-
Checker.MagicDRC,
93-
Magic.SpiceExtraction,
94-
Checker.IllegalOverlap,
95-
Netgen.LVS,
96-
Checker.LVS,
105+
# KLayout.XOR,
106+
# Checker.XOR,
107+
# Magic.DRC,
108+
# Checker.MagicDRC,
109+
# Magic.SpiceExtraction,
110+
# Checker.IllegalOverlap,
111+
# Netgen.LVS,
112+
# Checker.LVS,
97113
]
98114

99115

@@ -112,6 +128,7 @@ class TopFlow(SequentialFlow):
112128

113129
# Get PDK root out of environment
114130
PDK_ROOT = os.getenv('PDK_ROOT')
131+
PDK = os.getenv('PDK')
115132

116133
# Load TinyTapeout
117134
tti = tt.TinyTapeout()
@@ -137,9 +154,9 @@ class TopFlow(SequentialFlow):
137154
macros[m.mod_name].update({
138155
'nl': f'dir::verilog/{m.mod_name:s}.v',
139156
'spef': {
140-
"min_*": [ f'dir::spef/{m.mod_name:s}.min.spef' ],
157+
# "min_*": [ f'dir::spef/{m.mod_name:s}.min.spef' ],
141158
"nom_*": [ f'dir::spef/{m.mod_name:s}.nom.spef' ],
142-
"max_*": [ f'dir::spef/{m.mod_name:s}.max.spef' ],
159+
# "max_*": [ f'dir::spef/{m.mod_name:s}.max.spef' ],
143160
},
144161
})
145162

@@ -158,14 +175,14 @@ class TopFlow(SequentialFlow):
158175
# Custom config
159176
flow_cfg = {
160177
# Main design properties
161-
"DESIGN_NAME" : "openframe_project_wrapper",
178+
"DESIGN_NAME" : "tt_ihp_wrapper",
162179
"DESIGN_IS_CORE" : False,
163180

164181
# Sources
165182
"VERILOG_FILES": [
166-
"dir::openframe_project_wrapper.v",
183+
"dir::tt_ihp_wrapper.v",
167184
"dir::../../rtl/tt_top.v",
168-
"dir::../../rtl/tt_gpio.v",
185+
"dir::../../rtl/tt_ihp_gpio.v",
169186
"dir::../../rtl/tt_user_module.v",
170187
],
171188

@@ -175,6 +192,18 @@ class TopFlow(SequentialFlow):
175192
"MACROS": macros,
176193
"EXTRA_VERILOG_MODELS": [
177194
"dir::verilog/tt_um_all.v",
195+
# "pdk_dir::libs.ref/sg13g2_io/verilog/sg13g2_io.v", # FIXME
196+
],
197+
"EXTRA_LIBS": [
198+
"pdk_dir::libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib",
199+
],
200+
"EXTRA_LEFS": [
201+
"pdk_dir::libs.ref/sg13g2_io/lef/sg13g2_io.lef",
202+
"dir::lef/bondpad_70x70.lef",
203+
],
204+
"EXTRA_GDS_FILES": [
205+
"pdk_dir::libs.ref/sg13g2_io/gds/sg13g2_io.gds",
206+
"dir::gds/bondpad_70x70.gds",
178207
],
179208

180209
# Constraints
@@ -191,11 +220,11 @@ class TopFlow(SequentialFlow):
191220
"QUIT_ON_SYNTH_CHECKS" : False,
192221

193222
# Floorplanning
194-
"DIE_AREA" : [ 0.00, 0.00, 3166.63, 4766.63 ],
195-
"CORE_AREA" : [ 85.00, 85.00, 3081.63, 4681.63 ],
223+
"DIE_AREA" : [ 0.00, 0.00, 3600.00, 5000.00 ],
224+
"CORE_AREA" : [ 425.00, 425.00, 3175.00, 4575.00 ],
196225
"FP_SIZING" : "absolute",
197-
"FP_DEF_TEMPLATE" : "dir::openframe_project_wrapper.def",
198-
"FP_TEMPLATE_COPY_POWER_PINS" : True,
226+
# "FP_DEF_TEMPLATE" : "dir::openframe_project_wrapper.def",
227+
# "FP_TEMPLATE_COPY_POWER_PINS" : True,
199228

200229
# PDN
201230
"VDD_NETS": [ "vdpwr", "vapwr" ],
@@ -217,8 +246,8 @@ class TopFlow(SequentialFlow):
217246
# Routing
218247
"GRT_ALLOW_CONGESTION" : True,
219248
"GRT_REPAIR_ANTENNAS" : False,
220-
"GRT_LAYER_ADJUSTMENTS" : [1, 0.95, 0.95, 0, 0, 0],
221-
"RT_MAX_LAYER" : "met4",
249+
# "GRT_LAYER_ADJUSTMENTS" : [1, 0.95, 0.95, 0, 0, 0],
250+
"RT_MAX_LAYER" : "Metal5",
222251

223252
# Magic stream
224253
"MAGIC_ZEROIZE_ORIGIN" : False,
@@ -268,7 +297,7 @@ def pdn_align(x):
268297
flow_cfg,
269298
design_dir = ".",
270299
pdk_root = PDK_ROOT,
271-
pdk = "sky130A",
300+
pdk = PDK,
272301
)
273302

274303
flow.start(last_run = args.open_in_klayout)

‎ol2/tt_top/no_drc_cells.txt

-52
Original file line numberDiff line numberDiff line change
@@ -1,52 +0,0 @@
1-
sky130_fd_sc_hd__a2111oi_0
2-
sky130_fd_sc_hd__a21boi_0
3-
sky130_fd_sc_hd__and2_0
4-
sky130_fd_sc_hd__clkdlybuf4s15_1
5-
sky130_fd_sc_hd__clkdlybuf4s18_1
6-
sky130_fd_sc_hd__fa_4
7-
sky130_fd_sc_hd__lpflow_bleeder_1
8-
sky130_fd_sc_hd__lpflow_clkbufkapwr_1
9-
sky130_fd_sc_hd__lpflow_clkbufkapwr_16
10-
sky130_fd_sc_hd__lpflow_clkbufkapwr_2
11-
sky130_fd_sc_hd__lpflow_clkbufkapwr_4
12-
sky130_fd_sc_hd__lpflow_clkbufkapwr_8
13-
sky130_fd_sc_hd__lpflow_clkinvkapwr_1
14-
sky130_fd_sc_hd__lpflow_clkinvkapwr_16
15-
sky130_fd_sc_hd__lpflow_clkinvkapwr_2
16-
sky130_fd_sc_hd__lpflow_clkinvkapwr_4
17-
sky130_fd_sc_hd__lpflow_clkinvkapwr_8
18-
sky130_fd_sc_hd__lpflow_decapkapwr_12
19-
sky130_fd_sc_hd__lpflow_decapkapwr_3
20-
sky130_fd_sc_hd__lpflow_decapkapwr_4
21-
sky130_fd_sc_hd__lpflow_decapkapwr_6
22-
sky130_fd_sc_hd__lpflow_decapkapwr_8
23-
sky130_fd_sc_hd__lpflow_inputiso0n_1
24-
sky130_fd_sc_hd__lpflow_inputiso0p_1
25-
sky130_fd_sc_hd__lpflow_inputiso1n_1
26-
sky130_fd_sc_hd__lpflow_inputiso1p_1
27-
sky130_fd_sc_hd__lpflow_inputisolatch_1
28-
sky130_fd_sc_hd__lpflow_isobufsrc_1
29-
sky130_fd_sc_hd__lpflow_isobufsrc_16
30-
sky130_fd_sc_hd__lpflow_isobufsrc_2
31-
sky130_fd_sc_hd__lpflow_isobufsrc_4
32-
sky130_fd_sc_hd__lpflow_isobufsrc_8
33-
sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
34-
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
35-
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
36-
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
37-
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
38-
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
39-
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
40-
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4
41-
sky130_fd_sc_hd__mux4_4
42-
sky130_fd_sc_hd__o21ai_0
43-
sky130_fd_sc_hd__o311ai_0
44-
sky130_fd_sc_hd__or2_0
45-
sky130_fd_sc_hd__probe_p_8
46-
sky130_fd_sc_hd__probec_p_8
47-
sky130_fd_sc_hd__xor3_1
48-
sky130_fd_sc_hd__xor3_2
49-
sky130_fd_sc_hd__xor3_4
50-
sky130_fd_sc_hd__xnor3_1
51-
sky130_fd_sc_hd__xnor3_2
52-
sky130_fd_sc_hd__xnor3_4

‎ol2/tt_top/odb_power.py

+19-4
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,14 @@
1818

1919
import click
2020

21-
from reader import click_odb
21+
try:
22+
from reader import click_odb
23+
interactive = False
24+
except:
25+
sys.path.insert(0, os.path.join("/mnt/pdk/OL2/openlane2/openlane", "scripts", "odbpy"))
26+
interactive = True
27+
from reader import click_odb
28+
2229

2330

2431
@click.command()
@@ -31,18 +38,26 @@ def power(
3138
PDN = {
3239
'vgnd' : {
3340
'type' : 'GROUND',
34-
'pins' : [ 'VGND' ],
41+
'pins' : [ 'VGND', 'vss' ],
3542
},
3643
'vdpwr' : {
3744
'type' : 'POWER',
38-
'pins' : [ 'VPWR', 'VDPWR' ],
45+
'pins' : [ 'VPWR', 'VDPWR', 'vdd' ],
3946
'pg' : ( 'tt_pg_vdd_I', 'VPWR', 'GPWR' ),
4047
},
4148
'vapwr' : {
4249
'type' : 'POWER',
4350
'pins' : [ 'VAPWR' ],
4451
'pg' : ( 'tt_pg_vaa_I', 'VAPWR', 'GAPWR' ),
4552
},
53+
'iovss' : {
54+
'type' : 'GROUND',
55+
'pins' : [ 'iovss' ],
56+
},
57+
'iovdd' : {
58+
'type' : 'POWER',
59+
'pins' : [ 'iovdd' ],
60+
},
4661
}
4762

4863
# Load TinyTapeout
@@ -73,7 +88,7 @@ def power(
7388
is_pg = re.match(r'.*\.tt_pg_[\w_]*_I$', blk_inst.getName()) is not None
7489

7590
# Check if it's a user block
76-
is_um = blk_inst.getName().endswith('tt_um_I')
91+
is_um = blk_inst.getName().endswith('.tt_um_I')
7792

7893
# Scan all ITerms
7994
for iterm in blk_inst.getITerms():

‎ol2/tt_top/odb_route.py

+42-19
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,13 @@
1717

1818
import click
1919

20-
from reader import click_odb
20+
try:
21+
from reader import click_odb
22+
interactive = False
23+
except:
24+
sys.path.insert(0, os.path.join("/mnt/pdk/OL2/openlane2.ihp/openlane", "scripts", "odbpy"))
25+
interactive = True
26+
from reader import click_odb
2127

2228

2329
def getOtherITermsOnNet(it):
@@ -34,9 +40,9 @@ def __init__(self, reader, tti):
3440
# Find useful data
3541
tech = reader.db.getTech()
3642

37-
self.layer_h = tech.findLayer('met3')
38-
self.layer_v = tech.findLayer('met4')
39-
self.via = tech.findVia('M3M4_PR')
43+
self.layer_h = tech.findLayer('Metal4')
44+
self.layer_v = tech.findLayer('Metal5')
45+
self.via = tech.findVia('Via4_YX_so')
4046

4147
self.x_spine = []
4248
self.y_muxes = {}
@@ -237,8 +243,8 @@ def route_pad(self):
237243

238244
def route_um_tieoffs(self):
239245
# Get track info
240-
# We route horizontally on met4, non-preferred direction ...
241-
track_cfg = self.tti.cfg.pdk.tracks.met4.y
246+
# We route horizontally on Metal5, non-preferred direction ...
247+
track_cfg = self.tti.cfg.pdk.tracks.Metal5.y
242248

243249
def track_align(v):
244250
return track_cfg.offset + ((v - track_cfg.offset) // track_cfg.pitch) * track_cfg.pitch
@@ -1666,29 +1672,46 @@ def route(
16661672
# Load TinyTapeout
16671673
tti = tt.TinyTapeout(modules=False)
16681674

1675+
global interactive
1676+
if interactive:
1677+
import IPython
1678+
IPython.embed()
1679+
16691680
# Create router
16701681
r = Router(reader, tti)
16711682
r.route_vspine()
16721683
r.create_spine_obs()
16731684
r.create_macro_obs()
1674-
r.route_k01_global()
1675-
r.route_k01_gpio()
1676-
r.create_k01_obs()
1677-
r.route_pad()
1685+
#r.route_k01_global()
1686+
#r.route_k01_gpio()
1687+
#r.create_k01_obs()
1688+
#r.route_pad()
16781689
r.route_um_tieoffs()
16791690
r.route_um_signals()
16801691

1681-
# Create the module power straps
1682-
p = ModulePowerStrapper(reader, tti)
1683-
p.run()
1692+
## Create the module power straps
1693+
#p = ModulePowerStrapper(reader, tti)
1694+
#p.run()
1695+
1696+
## Create the ring power straps
1697+
#p = RingPowerStrapper(reader)
1698+
#p.run()
1699+
1700+
## Analog router
1701+
#a = AnalogRouter(reader, tti)
1702+
#a.run()
1703+
1704+
# Remove all BTerms that have no connections
1705+
bt_to_del = []
1706+
1707+
for bt in reader.block.getBTerms():
1708+
n = bt.getNet()
1709+
if (n.getITermCount() == 0) and (n.getBTermCount() == 1):
1710+
bt_to_del.append(bt)
16841711

1685-
# Create the ring power straps
1686-
p = RingPowerStrapper(reader)
1687-
p.run()
1712+
for bt in bt_to_del:
1713+
odb.dbBTerm.destroy(bt)
16881714

1689-
# Analog router
1690-
a = AnalogRouter(reader, tti)
1691-
a.run()
16921715

16931716
if __name__ == "__main__":
16941717
route()

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