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npigginmpe
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powerpc/32e: Ignore ESR in instruction storage interrupt handler
A e5500 machine running a 32-bit kernel sometimes hangs at boot, seemingly going into an infinite loop of instruction storage interrupts. The ESR (Exception Syndrome Register) has a value of 0x800000 (store) when this happens, which is likely set by a previous store. An instruction TLB miss interrupt would then leave ESR unchanged, and if no PTE exists it calls directly to the instruction storage interrupt handler without changing ESR. access_error() does not cause a segfault due to a store to a read-only vma because is_exec is true. Most subsequent fault handling does not check for a write fault on a read-only vma, and might do strange things like create a writeable PTE or call page_mkwrite on a read only vma or file. It's not clear what happens here to cause the infinite faulting in this case, a fault handler failure or low level PTE or TLB handling. In any case this can be fixed by having the instruction storage interrupt zero regs->dsisr rather than storing the ESR value to it. Fixes: a01a3f2 ("powerpc: remove arguments from fault handler functions") Cc: [email protected] # v5.12+ Reported-by: Jacques de Laval <[email protected]> Signed-off-by: Nicholas Piggin <[email protected]> Tested-by: Jacques de Laval <[email protected]> Reviewed-by: Christophe Leroy <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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arch/powerpc/kernel/head_booke.h

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -465,12 +465,21 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
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bl do_page_fault; \
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b interrupt_return
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/*
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* Instruction TLB Error interrupt handlers may call InstructionStorage
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* directly without clearing ESR, so the ESR at this point may be left over
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* from a prior interrupt.
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*
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* In any case, do_page_fault for BOOK3E does not use ESR and always expects
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* dsisr to be 0. ESR_DST from a prior store in particular would confuse fault
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* handling.
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*/
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#define INSTRUCTION_STORAGE_EXCEPTION \
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START_EXCEPTION(InstructionStorage) \
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NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \
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mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
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NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \
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li r5,0; /* Store 0 in regs->esr (dsisr) */ \
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stw r5,_ESR(r11); \
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stw r12, _DEAR(r11); /* Pass SRR0 as arg2 */ \
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stw r12, _DEAR(r11); /* Set regs->dear (dar) to SRR0 */ \
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prepare_transfer_to_handler; \
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bl do_page_fault; \
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b interrupt_return

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