@@ -55,52 +55,44 @@ object Cli {
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trait EmitFsdb { this : HasCliOptions =>
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addOption(
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- CliOption [Unit ](
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- name = " emitFsdb" ,
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- help = " compile with FSDB waveform support and start dumping waves at time zero" ,
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- convert = value => {
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- val trueValue = Set (" true" , " 1" )
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- trueValue.contains(value) match {
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- case true => ()
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- case false =>
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- throw new IllegalArgumentException (
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- s """ invalid argument ' $value' for option 'emitFsdb', must be one of ${trueValue
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- .mkString(" [" , " , " , " ]" )}"""
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- ) with NoStackTrace
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- }
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- },
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- updateChiselOptions = (_, a) => a,
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- updateFirtoolOptions = (_, a) => a,
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- updateCommonSettings = (_, options) => {
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- options.copy(
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- verilogPreprocessorDefines =
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- options.verilogPreprocessorDefines :+ VerilogPreprocessorDefine (enableFsdbTracingSupport),
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- simulationSettings = options.simulationSettings.copy(
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- enableWavesAtTimeZero = true
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+ CliOption
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+ .flag(
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+ name = " emitFsdb" ,
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+ help = " compile with FSDB waveform support and start dumping waves at time zero"
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+ )
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+ .copy[Unit ](
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+ updateChiselOptions = (_, a) => a,
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+ updateFirtoolOptions = (_, a) => a,
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+ updateCommonSettings = (_, options) => {
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+ options.copy(
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+ verilogPreprocessorDefines =
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+ options.verilogPreprocessorDefines :+ VerilogPreprocessorDefine (enableFsdbTracingSupport),
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+ simulationSettings = options.simulationSettings.copy(
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+ enableWavesAtTimeZero = true
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+ )
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)
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- )
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- },
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- updateBackendSettings = (_, options) =>
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- options match {
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- case options : svsim.vcs. Backend . CompilationSettings =>
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- options.copy(
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- traceSettings = options.traceSettings.copy(fsdbSettings =
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- Some (
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- svsim.vcs. Backend . CompilationSettings . TraceSettings . FsdbSettings (
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- sys.env.getOrElse(
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- " VERDI_HOME " ,
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- throw new RuntimeException (
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- " Cannot enable FSDB support as the environment variable 'VERDI_HOME' was not set. "
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+ },
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+ updateBackendSettings = (_, options) =>
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+ options match {
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+ case options : svsim.vcs. Backend . CompilationSettings =>
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+ options.copy(
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+ traceSettings = options.traceSettings. copy(fsdbSettings =
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+ Some (
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+ svsim.vcs. Backend . CompilationSettings . TraceSettings . FsdbSettings (
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+ sys.env.getOrElse (
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+ " VERDI_HOME " ,
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+ throw new RuntimeException (
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+ " Cannot enable FSDB support as the environment variable 'VERDI_HOME' was not set. "
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+ )
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)
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)
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)
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)
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)
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- )
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- case options : svsim.verilator.Backend .CompilationSettings =>
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- throw new IllegalArgumentException (" Verilator does not support FSDB waveforms." )
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- }
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- )
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+ case options : svsim.verilator.Backend .CompilationSettings =>
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+ throw new IllegalArgumentException (" Verilator does not support FSDB waveforms." )
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+ }
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+ )
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)
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}
@@ -115,46 +107,36 @@ object Cli {
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trait EmitVcd { this : HasCliOptions =>
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addOption(
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- CliOption [Unit ](
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- name = " emitVcd" ,
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- help = " compile with VCD waveform support and start dumping waves at time zero" ,
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- convert = value => {
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- val trueValue = Set (" true" , " 1" )
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- trueValue.contains(value) match {
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- case true => ()
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- case false =>
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- throw new IllegalArgumentException (
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- s """ invalid argument ' $value' for option 'emitVcd', must be one of ${trueValue
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- .mkString(" [" , " , " , " ]" )}"""
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- ) with NoStackTrace
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- }
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- },
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- updateChiselOptions = (_, a) => a,
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- updateFirtoolOptions = (_, a) => a,
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- updateCommonSettings = (_, options) => {
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- options.copy(
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- verilogPreprocessorDefines =
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- options.verilogPreprocessorDefines :+ VerilogPreprocessorDefine (enableVcdTracingSupport),
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- simulationSettings = options.simulationSettings.copy(
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- enableWavesAtTimeZero = true
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- )
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- )
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- },
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- updateBackendSettings = (_, options) =>
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- options match {
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- case options : svsim.vcs.Backend .CompilationSettings =>
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- options.copy(
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- traceSettings = options.traceSettings.copy(enableVcd = true )
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+ CliOption
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+ .flag(name = " emitVcd" , help = " compile with VCD waveform support and start dumping waves at time zero" )
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+ .copy[Unit ](
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+ updateChiselOptions = (_, a) => a,
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+ updateFirtoolOptions = (_, a) => a,
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+ updateCommonSettings = (_, options) => {
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+ options.copy(
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+ verilogPreprocessorDefines =
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+ options.verilogPreprocessorDefines :+ VerilogPreprocessorDefine (enableVcdTracingSupport),
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+ simulationSettings = options.simulationSettings.copy(
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+ enableWavesAtTimeZero = true
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)
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- case options : svsim.verilator.Backend .CompilationSettings =>
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- options.copy(
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- traceStyle = options.traceStyle match {
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- case None => Some (svsim.verilator.Backend .CompilationSettings .TraceStyle .Vcd (filename = " trace.vcd" ))
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- case alreadySet => alreadySet
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- }
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- )
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- }
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- )
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+ )
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+ },
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+ updateBackendSettings = (_, options) =>
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+ options match {
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+ case options : svsim.vcs.Backend .CompilationSettings =>
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+ options.copy(
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+ traceSettings = options.traceSettings.copy(enableVcd = true )
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+ )
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+ case options : svsim.verilator.Backend .CompilationSettings =>
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+ options.copy(
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+ traceStyle = options.traceStyle match {
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+ case None =>
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+ Some (svsim.verilator.Backend .CompilationSettings .TraceStyle .Vcd (filename = " trace.vcd" ))
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+ case alreadySet => alreadySet
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+ }
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+ )
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+ }
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+ )
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)
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}
@@ -172,41 +154,33 @@ object Cli {
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trait EmitVpd { this : HasCliOptions =>
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addOption(
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- CliOption [Unit ](
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- name = " emitVpd" ,
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- help = " compile with VPD waveform support and start dumping waves at time zero" ,
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- convert = value => {
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- val trueValue = Set (" true" , " 1" )
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- trueValue.contains(value) match {
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- case true => ()
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- case false =>
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- throw new IllegalArgumentException (
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- s """ invalid argument ' $value' for option 'emitVpd', must be one of ${trueValue
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- .mkString(" [" , " , " , " ]" )}"""
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- ) with NoStackTrace
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- }
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- },
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- updateChiselOptions = (_, a) => a,
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- updateFirtoolOptions = (_, a) => a,
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- updateCommonSettings = (_, options) => {
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- options.copy(
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- verilogPreprocessorDefines =
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- options.verilogPreprocessorDefines :+ VerilogPreprocessorDefine (enableVpdTracingSupport),
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- simulationSettings = options.simulationSettings.copy(
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- enableWavesAtTimeZero = true
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- )
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- )
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- },
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- updateBackendSettings = (_, options) =>
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- options match {
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- case options : svsim.vcs.Backend .CompilationSettings =>
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- options.copy(
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- traceSettings = options.traceSettings.copy(enableVpd = true )
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+ CliOption
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+ .flag(
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+ name = " emitVpd" ,
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+ help = " compile with VPD waveform support and start dumping waves at time zero"
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+ )
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+ .copy[Unit ](
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+ updateChiselOptions = (_, a) => a,
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+ updateFirtoolOptions = (_, a) => a,
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+ updateCommonSettings = (_, options) => {
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+ options.copy(
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+ verilogPreprocessorDefines =
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+ options.verilogPreprocessorDefines :+ VerilogPreprocessorDefine (enableVpdTracingSupport),
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+ simulationSettings = options.simulationSettings.copy(
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+ enableWavesAtTimeZero = true
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)
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- case options : svsim.verilator.Backend .CompilationSettings =>
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- throw new IllegalArgumentException (" Verilator does not support VPD waveforms." )
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- }
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- )
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+ )
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+ },
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+ updateBackendSettings = (_, options) =>
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+ options match {
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+ case options : svsim.vcs.Backend .CompilationSettings =>
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+ options.copy(
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+ traceSettings = options.traceSettings.copy(enableVpd = true )
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+ )
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+ case options : svsim.verilator.Backend .CompilationSettings =>
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+ throw new IllegalArgumentException (" Verilator does not support VPD waveforms." )
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+ }
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+ )
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)
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}
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