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dernasherbrezondernasherbrezon
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make sure fist argument in test is "expected" value
1 parent e11c056 commit 4ccb5e0

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+86
-86
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1 file changed

+86
-86
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‎test/test_sx127x.c

+86-86
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ void test_fsk_ook_rx() {
136136
spi_mock_fifo(payload, 64, SX127X_OK);
137137
registers[0x3f] = 0b00000100; // payload_ready
138138
sx127x_handle_interrupt(device);
139-
TEST_ASSERT_EQUAL_INT(registers[0x3f], 0b00010000); // fifo_overrun
139+
TEST_ASSERT_EQUAL_INT(0b00010000, registers[0x3f]); // fifo_overrun
140140
TEST_ASSERT_EQUAL_INT(0, rx_callback_data_length);
141141

142142
// 10. Small payload with ignored CRC
@@ -158,29 +158,29 @@ void test_fsk_ook_beacon() {
158158
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_packet_format(SX127X_FIXED, sizeof(data), device));
159159
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_tx_start_beacon(data, sizeof(data), 1000, device));
160160
spi_assert_write(data, sizeof(data));
161-
TEST_ASSERT_EQUAL_INT(registers[0x39], 243);
162-
TEST_ASSERT_EQUAL_INT(registers[0x3a], 57);
163-
TEST_ASSERT_EQUAL_INT(registers[0x38], 0b00001001);
161+
TEST_ASSERT_EQUAL_INT(243, registers[0x39]);
162+
TEST_ASSERT_EQUAL_INT(57, registers[0x3a]);
163+
TEST_ASSERT_EQUAL_INT(0b00001001, registers[0x38]);
164164

165-
TEST_ASSERT_EQUAL_INT(registers[0x35], 0b10011111);
166-
TEST_ASSERT_EQUAL_INT(registers[0x3f], 0b00010000);
167-
TEST_ASSERT_EQUAL_INT(registers[0x31], 0b00001000);
168-
TEST_ASSERT_EQUAL_INT(registers[0x36], 0b10100100); // sequencer
165+
TEST_ASSERT_EQUAL_INT(0b10011111, registers[0x35]);
166+
TEST_ASSERT_EQUAL_INT(0b00010000, registers[0x3f]);
167+
TEST_ASSERT_EQUAL_INT(0b00001000, registers[0x31]);
168+
TEST_ASSERT_EQUAL_INT(0b10100100, registers[0x36]); // sequencer
169169

170170
// test different timer settings
171171
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_tx_start_beacon(data, sizeof(data), 15, device));
172-
TEST_ASSERT_EQUAL_INT(registers[0x39], 234);
173-
TEST_ASSERT_EQUAL_INT(registers[0x3a], 0);
174-
TEST_ASSERT_EQUAL_INT(registers[0x38], 0b00000111);
172+
TEST_ASSERT_EQUAL_INT(234, registers[0x39]);
173+
TEST_ASSERT_EQUAL_INT(0, registers[0x3a]);
174+
TEST_ASSERT_EQUAL_INT(0b00000111, registers[0x38]);
175175
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_tx_start_beacon(data, sizeof(data), 20, device));
176-
TEST_ASSERT_EQUAL_INT(registers[0x39], 156);
177-
TEST_ASSERT_EQUAL_INT(registers[0x3a], 156);
178-
TEST_ASSERT_EQUAL_INT(registers[0x38], 0b00000101);
176+
TEST_ASSERT_EQUAL_INT(156, registers[0x39]);
177+
TEST_ASSERT_EQUAL_INT(156, registers[0x3a]);
178+
TEST_ASSERT_EQUAL_INT(0b00000101, registers[0x38]);
179179

180180
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_tx_stop_beacon(device));
181-
TEST_ASSERT_EQUAL_INT(registers[0x36], 0b01000000); //stop sequencer
182-
TEST_ASSERT_EQUAL_INT(registers[0x3f], 0b00010000);
183-
TEST_ASSERT_EQUAL_INT(registers[0x31], 0b00000000);
181+
TEST_ASSERT_EQUAL_INT(0b01000000, registers[0x36]); //stop sequencer
182+
TEST_ASSERT_EQUAL_INT(0b00010000, registers[0x3f]);
183+
TEST_ASSERT_EQUAL_INT(0b00000000, registers[0x31]);
184184
}
185185

186186
void test_fsk_ook_tx() {
@@ -314,12 +314,12 @@ void test_lora_tx() {
314314
payload[i] = i;
315315
}
316316
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_tx_set_for_transmission(payload, sizeof(payload), device));
317-
TEST_ASSERT_EQUAL_INT(registers[0x0d], 0x00);
318-
TEST_ASSERT_EQUAL_INT(registers[0x22], sizeof(payload));
317+
TEST_ASSERT_EQUAL_INT(0x00, registers[0x0d]);
318+
TEST_ASSERT_EQUAL_INT(sizeof(payload), registers[0x22]);
319319
spi_assert_write(payload, sizeof(payload));
320320

321321
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_TX, SX127x_MODULATION_LORA, device));
322-
TEST_ASSERT_EQUAL_INT(registers[0x40], 0b01010000);
322+
TEST_ASSERT_EQUAL_INT(0b01010000, registers[0x40]);
323323

324324
// simulate interrupt
325325
registers[0x12] = 0b00001000; // tx done
@@ -329,7 +329,7 @@ void test_lora_tx() {
329329

330330
void test_lora_rx() {
331331
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_RX_CONT, SX127x_MODULATION_LORA, device));
332-
TEST_ASSERT_EQUAL_INT(registers[0x40], 0b00000000);
332+
TEST_ASSERT_EQUAL_INT(0b00000000, registers[0x40]);
333333
uint8_t payload[255];
334334
for (int i = 0; i < sizeof(payload); i++) {
335335
payload[i] = i;
@@ -348,17 +348,17 @@ void test_lora_rx() {
348348
.enable_crc = true,
349349
.length = 2};
350350
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_set_implicit_header(&header, device));
351-
TEST_ASSERT_EQUAL_INT(registers[0x1d], 0b00000011);
352-
TEST_ASSERT_EQUAL_INT(registers[0x22], header.length);
353-
TEST_ASSERT_EQUAL_INT(registers[0x1e], 0b00000100);
351+
TEST_ASSERT_EQUAL_INT(0b00000011, registers[0x1d]);
352+
TEST_ASSERT_EQUAL_INT(header.length, registers[0x22]);
353+
TEST_ASSERT_EQUAL_INT(0b00000100, registers[0x1e]);
354354
spi_mock_fifo(payload, sizeof(payload), SX127X_OK);
355355
sx127x_handle_interrupt(device);
356356
TEST_ASSERT_EQUAL_INT(header.length, rx_callback_data_length);
357357
}
358358

359359
void test_lora_cad() {
360360
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_CAD, SX127x_MODULATION_LORA, device));
361-
TEST_ASSERT_EQUAL_INT(registers[0x40], 0b10000000);
361+
TEST_ASSERT_EQUAL_INT(0b10000000, registers[0x40]);
362362
sx127x_lora_cad_set_callback(cad_callback, device);
363363
registers[0x12] = 0b00000101; // cad detected
364364
sx127x_handle_interrupt(device);
@@ -376,7 +376,7 @@ void test_fsk_ook_rssi() {
376376
TEST_ASSERT_EQUAL_INT(SX127X_ERR_NOT_FOUND, sx127x_rx_get_packet_rssi(device, &rssi));
377377

378378
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_RX_CONT, SX127x_MODULATION_FSK, device));
379-
TEST_ASSERT_EQUAL_INT(registers[0x41], 0b11000001);
379+
TEST_ASSERT_EQUAL_INT(0b11000001, registers[0x41]);
380380

381381
// simulate interrupt
382382
registers[0x3e] = 0b00000010;
@@ -405,77 +405,77 @@ void test_fsk_ook_rssi() {
405405

406406
void test_fsk_ook() {
407407
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_SLEEP, SX127x_MODULATION_FSK, device));
408-
TEST_ASSERT_EQUAL_INT(registers[0x01], 0b00000000);
408+
TEST_ASSERT_EQUAL_INT(0b00000000, registers[0x01]);
409409
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_frequency(437200012, device));
410-
TEST_ASSERT_EQUAL_INT(registers[0x06], 0x6d);
411-
TEST_ASSERT_EQUAL_INT(registers[0x07], 0x4c);
412-
TEST_ASSERT_EQUAL_INT(registers[0x08], 0xcd);
410+
TEST_ASSERT_EQUAL_INT(0x6d, registers[0x06]);
411+
TEST_ASSERT_EQUAL_INT(0x4c, registers[0x07]);
412+
TEST_ASSERT_EQUAL_INT(0xcd, registers[0x08]);
413413
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_rx_set_lna_gain(SX127x_LNA_GAIN_G4, device));
414414
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_bitrate(4800.0, device));
415-
TEST_ASSERT_EQUAL_INT(registers[0x02], 0x1A);
416-
TEST_ASSERT_EQUAL_INT(registers[0x03], 0x0A);
417-
TEST_ASSERT_EQUAL_INT(registers[0x5d], 0x0A);
415+
TEST_ASSERT_EQUAL_INT(0x1A, registers[0x02]);
416+
TEST_ASSERT_EQUAL_INT(0x0A, registers[0x03]);
417+
TEST_ASSERT_EQUAL_INT(0x0A, registers[0x5d]);
418418
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_set_fdev(5000.0, device));
419-
TEST_ASSERT_EQUAL_INT(registers[0x04], 0x00);
420-
TEST_ASSERT_EQUAL_INT(registers[0x05], 0x51);
419+
TEST_ASSERT_EQUAL_INT(0x00, registers[0x04]);
420+
TEST_ASSERT_EQUAL_INT(0x51, registers[0x05]);
421421
uint8_t syncWord[] = {0x12, 0xAD};
422422
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_syncword(syncWord, 2, device));
423-
TEST_ASSERT_EQUAL_INT(registers[0x28], 0x12);
424-
TEST_ASSERT_EQUAL_INT(registers[0x29], 0xAD);
423+
TEST_ASSERT_EQUAL_INT(0x12, registers[0x28]);
424+
TEST_ASSERT_EQUAL_INT(0xAD, registers[0x29]);
425425
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_packet_encoding(SX127X_SCRAMBLED, device));
426426
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_crc(SX127X_CRC_CCITT, device));
427427
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_address_filtering(SX127X_FILTER_NODE_AND_BROADCAST, 0x11, 0x12, device));
428-
TEST_ASSERT_EQUAL_INT(registers[0x33], 0x11);
429-
TEST_ASSERT_EQUAL_INT(registers[0x34], 0x12);
428+
TEST_ASSERT_EQUAL_INT(0x11, registers[0x33]);
429+
TEST_ASSERT_EQUAL_INT(0x12, registers[0x34]);
430430
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_packet_format(SX127X_VARIABLE, 255, device));
431-
TEST_ASSERT_EQUAL_INT(registers[0x31], 0b00000000);
432-
TEST_ASSERT_EQUAL_INT(registers[0x32], 0xFF);
431+
TEST_ASSERT_EQUAL_INT(0b00000000, registers[0x31]);
432+
TEST_ASSERT_EQUAL_INT(0xFF, registers[0x32]);
433433
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_set_data_shaping(SX127X_BT_0_5, SX127X_PA_RAMP_10, device));
434434
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_preamble_type(SX127X_PREAMBLE_55, device));
435435
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_set_afc_auto(true, device));
436436
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_set_afc_bandwidth(20000.0, device));
437-
TEST_ASSERT_EQUAL_INT(registers[0x13], 0x14);
437+
TEST_ASSERT_EQUAL_INT(0x14, registers[0x13]);
438438
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_set_bandwidth(5000.0, device));
439-
TEST_ASSERT_EQUAL_INT(registers[0x12], 0x16);
439+
TEST_ASSERT_EQUAL_INT(0x16, registers[0x12]);
440440
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_set_rssi_config(SX127X_8, 0, device));
441441
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_set_collision_restart(true, 10, device));
442-
TEST_ASSERT_EQUAL_INT(registers[0x0f], 10);
442+
TEST_ASSERT_EQUAL_INT(10, registers[0x0f]);
443443
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_set_trigger(SX127X_RX_TRIGGER_RSSI_PREAMBLE, device));
444444
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_set_preamble_detector(true, 2, 0x0A, device));
445-
TEST_ASSERT_EQUAL_INT(registers[0x30], 0b11011100);
445+
TEST_ASSERT_EQUAL_INT(0b11011100, registers[0x30]);
446446

447447
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_packet_format(SX127X_FIXED, 2047, device));
448-
TEST_ASSERT_EQUAL_INT(registers[0x31], 0b00000111);
449-
TEST_ASSERT_EQUAL_INT(registers[0x32], 0xFF);
448+
TEST_ASSERT_EQUAL_INT(0b00000111, registers[0x31]);
449+
TEST_ASSERT_EQUAL_INT(0xFF, registers[0x32]);
450450

451451
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_SLEEP, SX127x_MODULATION_OOK, device));
452452
TEST_ASSERT_EQUAL_INT(SX127X_ERR_INVALID_ARG, sx127x_fsk_ook_set_bitrate(800, device));
453453
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_bitrate(4800.0, device));
454-
TEST_ASSERT_EQUAL_INT(registers[0x02], 0x1A);
455-
TEST_ASSERT_EQUAL_INT(registers[0x03], 0x0A);
454+
TEST_ASSERT_EQUAL_INT(0x1A, registers[0x02]);
455+
TEST_ASSERT_EQUAL_INT(0x0A, registers[0x03]);
456456
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_ook_rx_set_peak_mode(SX127X_0_5_DB, 0x0C, SX127X_1_1_CHIP, device));
457457

458-
TEST_ASSERT_EQUAL_INT(registers[0x0d], 0b10010111);
459-
TEST_ASSERT_EQUAL_INT(registers[0x0c], 0b10000000);
460-
TEST_ASSERT_EQUAL_INT(registers[0x27], 0b01110001);
461-
TEST_ASSERT_EQUAL_INT(registers[0x0a], 0b01001001);
462-
TEST_ASSERT_EQUAL_INT(registers[0x0e], 0b00000010);
463-
TEST_ASSERT_EQUAL_INT(registers[0x1f], 0b10101010);
458+
TEST_ASSERT_EQUAL_INT(0b10010111, registers[0x0d]);
459+
TEST_ASSERT_EQUAL_INT(0b10000000, registers[0x0c]);
460+
TEST_ASSERT_EQUAL_INT(0b01110001, registers[0x27]);
461+
TEST_ASSERT_EQUAL_INT(0b01001001, registers[0x0a]);
462+
TEST_ASSERT_EQUAL_INT(0b00000010, registers[0x0e]);
463+
TEST_ASSERT_EQUAL_INT(0b10101010, registers[0x1f]);
464464

465465
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_ook_set_data_shaping(SX127X_1_BIT_RATE, SX127X_PA_RAMP_10, device));
466-
TEST_ASSERT_EQUAL_INT(registers[0x0a], 0b00101001);
466+
TEST_ASSERT_EQUAL_INT(0b00101001, registers[0x0a]);
467467

468468
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_ook_rx_set_fixed_mode(0x11, device));
469-
TEST_ASSERT_EQUAL_INT(registers[0x14], 0b00000000);
470-
TEST_ASSERT_EQUAL_INT(registers[0x15], 0x11);
469+
TEST_ASSERT_EQUAL_INT(0b00000000, registers[0x14]);
470+
TEST_ASSERT_EQUAL_INT(0x11, registers[0x15]);
471471

472472
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_ook_rx_set_avg_mode(SX127X_2_DB, SX127X_4_PI, device));
473-
TEST_ASSERT_EQUAL_INT(registers[0x14], 0b00010000);
474-
TEST_ASSERT_EQUAL_INT(registers[0x16], 0b00000110);
473+
TEST_ASSERT_EQUAL_INT(0b00010000, registers[0x14]);
474+
TEST_ASSERT_EQUAL_INT(0b00000110, registers[0x16]);
475475

476476
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_preamble_length(8, device));
477-
TEST_ASSERT_EQUAL_INT(registers[0x25], 0x00);
478-
TEST_ASSERT_EQUAL_INT(registers[0x26], 0x08);
477+
TEST_ASSERT_EQUAL_INT(0x00, registers[0x25]);
478+
TEST_ASSERT_EQUAL_INT(0x08, registers[0x26]);
479479

480480
registers[0x1b] = 0xFF;
481481
registers[0x1c] = 0xF0;
@@ -487,7 +487,7 @@ void test_fsk_ook() {
487487
TEST_ASSERT_EQUAL_INT(SX127X_ERR_INVALID_STATE, sx127x_fsk_ook_rx_calibrate(device));
488488
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_STANDBY, SX127x_MODULATION_FSK, device));
489489
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_rx_calibrate(device));
490-
TEST_ASSERT_EQUAL_INT(registers[0x3b], 0b01000000); // start calibration attempted
490+
TEST_ASSERT_EQUAL_INT(0b01000000, registers[0x3b]); // start calibration attempted
491491

492492
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_rx_set_lna_gain(SX127x_LNA_GAIN_AUTO, device));
493493
TEST_ASSERT_EQUAL_INT(registers[0x0d], 0b10011111); // + previous configuration
@@ -501,19 +501,19 @@ void test_fsk_ook() {
501501
TEST_ASSERT_EQUAL_INT(11, raw_temperature);
502502

503503
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_fsk_ook_set_temp_monitor(false, device));
504-
TEST_ASSERT_EQUAL_INT(registers[0x3b], 0b01000001); // + previous configuration
504+
TEST_ASSERT_EQUAL_INT(0b01000001, registers[0x3b]); // + previous configuration
505505
}
506506

507507
void test_lora() {
508508
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_opmod(SX127x_MODE_SLEEP, SX127x_MODULATION_LORA, device));
509-
TEST_ASSERT_EQUAL_INT(registers[0x01], 0b10000000);
509+
TEST_ASSERT_EQUAL_INT(0b10000000, registers[0x01]);
510510
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_set_frequency(437200012, device));
511-
TEST_ASSERT_EQUAL_INT(registers[0x06], 0x6d);
512-
TEST_ASSERT_EQUAL_INT(registers[0x07], 0x4c);
513-
TEST_ASSERT_EQUAL_INT(registers[0x08], 0xcd);
511+
TEST_ASSERT_EQUAL_INT(0x6d, registers[0x06]);
512+
TEST_ASSERT_EQUAL_INT(0x4c, registers[0x07]);
513+
TEST_ASSERT_EQUAL_INT(0xcd, registers[0x08]);
514514
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_reset_fifo(device));
515-
TEST_ASSERT_EQUAL_INT(registers[0x0e], 0x00);
516-
TEST_ASSERT_EQUAL_INT(registers[0x0f], 0x00);
515+
TEST_ASSERT_EQUAL_INT(0x00, registers[0x0e]);
516+
TEST_ASSERT_EQUAL_INT(0x00, registers[0x0f]);
517517
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_set_bandwidth(SX127x_BW_125000, device));
518518
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_set_implicit_header(NULL, device));
519519
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_set_modem_config_2(SX127x_SF_9, device));
@@ -524,18 +524,18 @@ void test_lora() {
524524
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_rx_set_lna_gain(SX127x_LNA_GAIN_G4, device));
525525
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_tx_set_pa_config(SX127x_PA_PIN_BOOST, 4, device));
526526

527-
TEST_ASSERT_EQUAL_INT(registers[0x1d], 0b01110000);
528-
TEST_ASSERT_EQUAL_INT(registers[0x31], 0xc3);
529-
TEST_ASSERT_EQUAL_INT(registers[0x37], 0x0a);
530-
TEST_ASSERT_EQUAL_INT(registers[0x1e], 0b10010000);
531-
TEST_ASSERT_EQUAL_INT(registers[0x39], 18);
532-
TEST_ASSERT_EQUAL_INT(registers[0x20], 0);
533-
TEST_ASSERT_EQUAL_INT(registers[0x21], 8);
534-
TEST_ASSERT_EQUAL_INT(registers[0x26], 0b00001000);
535-
TEST_ASSERT_EQUAL_INT(registers[0x0c], 0b10000011);
536-
TEST_ASSERT_EQUAL_INT(registers[0x4d], 0b10000100);
537-
TEST_ASSERT_EQUAL_INT(registers[0x09], 0b10000010);
538-
TEST_ASSERT_EQUAL_INT(registers[0x0b], 0x28);
527+
TEST_ASSERT_EQUAL_INT(0b01110000, registers[0x1d]);
528+
TEST_ASSERT_EQUAL_INT(0xc3, registers[0x31]);
529+
TEST_ASSERT_EQUAL_INT(0x0a, registers[0x37]);
530+
TEST_ASSERT_EQUAL_INT(0b10010000, registers[0x1e]);
531+
TEST_ASSERT_EQUAL_INT(18, registers[0x39]);
532+
TEST_ASSERT_EQUAL_INT(0, registers[0x20]);
533+
TEST_ASSERT_EQUAL_INT(8, registers[0x21]);
534+
TEST_ASSERT_EQUAL_INT(0b00001000, registers[0x26]);
535+
TEST_ASSERT_EQUAL_INT(0b10000011, registers[0x0c]);
536+
TEST_ASSERT_EQUAL_INT(0b10000100, registers[0x4d]);
537+
TEST_ASSERT_EQUAL_INT(0b10000010, registers[0x09]);
538+
TEST_ASSERT_EQUAL_INT(0x28, registers[0x0b]);
539539

540540
uint32_t bandwidth;
541541
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_get_bandwidth(device, &bandwidth));
@@ -562,14 +562,14 @@ void test_lora() {
562562
.enable_crc = true,
563563
.coding_rate = SX127x_CR_4_5};
564564
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_tx_set_explicit_header(&header, device));
565-
TEST_ASSERT_EQUAL_INT(registers[0x1d], 0b01110010);
566-
TEST_ASSERT_EQUAL_INT(registers[0x1e], 0b10010100);
565+
TEST_ASSERT_EQUAL_INT(0b01110010, registers[0x1d]);
566+
TEST_ASSERT_EQUAL_INT(0b10010100, registers[0x1e]);
567567

568568
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_lora_set_ppm_offset(4000, device));
569-
TEST_ASSERT_EQUAL_INT(registers[0x27], 8);
569+
TEST_ASSERT_EQUAL_INT(8, registers[0x27]);
570570

571571
TEST_ASSERT_EQUAL_INT(SX127X_OK, sx127x_rx_set_lna_gain(SX127x_LNA_GAIN_AUTO, device));
572-
TEST_ASSERT_EQUAL_INT(registers[0x26], 0b00001100); // + previous config
572+
TEST_ASSERT_EQUAL_INT(0b00001100, registers[0x26]); // + previous config
573573
}
574574

575575
void test_init_failure() {

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