@@ -77,15 +77,74 @@ void Translator::EmitPrologue() {
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ir.SetVectorReg (IR::VectorReg::V3, ir.GetAttributeU32 (IR::Attribute::PrimitiveId));
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break ;
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case LogicalStage::Fragment:
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- // https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L258
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- // The first two VGPRs are used for i/j barycentric coordinates. In the vast majority of
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- // cases it will be only those two, but if shader is using both e.g linear and perspective
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- // inputs it can be more For now assume that this isn't the case.
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- dst_vreg = IR::VectorReg::V2;
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- for (u32 i = 0 ; i < 4 ; i++) {
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- ir.SetVectorReg (dst_vreg++, ir.GetAttribute (IR::Attribute::FragCoord, i));
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+ dst_vreg = IR::VectorReg::V0;
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+ if (runtime_info.fs_info .addr_flags .persp_sample_ena ) {
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+ ++dst_vreg; // I
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+ ++dst_vreg; // J
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+ }
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+ if (runtime_info.fs_info .addr_flags .persp_center_ena ) {
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+ ++dst_vreg; // I
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+ ++dst_vreg; // J
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+ }
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+ if (runtime_info.fs_info .addr_flags .persp_centroid_ena ) {
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+ ++dst_vreg; // I
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+ ++dst_vreg; // J
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+ }
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+ if (runtime_info.fs_info .addr_flags .persp_pull_model_ena ) {
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+ ++dst_vreg; // I/W
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+ ++dst_vreg; // J/W
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+ ++dst_vreg; // 1/W
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+ }
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+ if (runtime_info.fs_info .addr_flags .linear_sample_ena ) {
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+ ++dst_vreg; // I
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+ ++dst_vreg; // J
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+ }
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+ if (runtime_info.fs_info .addr_flags .linear_center_ena ) {
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+ ++dst_vreg; // I
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+ ++dst_vreg; // J
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+ }
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+ if (runtime_info.fs_info .addr_flags .linear_centroid_ena ) {
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+ ++dst_vreg; // I
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+ ++dst_vreg; // J
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+ }
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+ if (runtime_info.fs_info .addr_flags .line_stipple_tex_ena ) {
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+ ++dst_vreg;
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+ }
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+ if (runtime_info.fs_info .addr_flags .pos_x_float_ena ) {
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+ if (runtime_info.fs_info .en_flags .pos_x_float_ena ) {
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+ ir.SetVectorReg (dst_vreg++, ir.GetAttribute (IR::Attribute::FragCoord, 0 ));
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+ } else {
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+ ir.SetVectorReg (dst_vreg++, ir.Imm32 (0 .0f ));
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+ }
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+ }
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+ if (runtime_info.fs_info .addr_flags .pos_y_float_ena ) {
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+ if (runtime_info.fs_info .en_flags .pos_y_float_ena ) {
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+ ir.SetVectorReg (dst_vreg++, ir.GetAttribute (IR::Attribute::FragCoord, 1 ));
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+ } else {
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+ ir.SetVectorReg (dst_vreg++, ir.Imm32 (0 .0f ));
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+ }
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+ }
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+ if (runtime_info.fs_info .addr_flags .pos_z_float_ena ) {
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+ if (runtime_info.fs_info .en_flags .pos_z_float_ena ) {
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+ ir.SetVectorReg (dst_vreg++, ir.GetAttribute (IR::Attribute::FragCoord, 2 ));
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+ } else {
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+ ir.SetVectorReg (dst_vreg++, ir.Imm32 (0 .0f ));
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+ }
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+ }
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+ if (runtime_info.fs_info .addr_flags .pos_w_float_ena ) {
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+ if (runtime_info.fs_info .en_flags .pos_w_float_ena ) {
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+ ir.SetVectorReg (dst_vreg++, ir.GetAttribute (IR::Attribute::FragCoord, 3 ));
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+ } else {
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+ ir.SetVectorReg (dst_vreg++, ir.Imm32 (0 .0f ));
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+ }
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+ }
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+ if (runtime_info.fs_info .addr_flags .front_face_ena ) {
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+ if (runtime_info.fs_info .en_flags .front_face_ena ) {
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+ ir.SetVectorReg (dst_vreg++, ir.GetAttributeU32 (IR::Attribute::IsFrontFace));
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+ } else {
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+ ir.SetVectorReg (dst_vreg++, ir.Imm32 (0 ));
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+ }
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}
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- ir.SetVectorReg (dst_vreg++, ir.GetAttributeU32 (IR::Attribute::IsFrontFace));
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break ;
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case LogicalStage::Compute:
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ir.SetVectorReg (dst_vreg++, ir.GetAttributeU32 (IR::Attribute::LocalInvocationId, 0 ));
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