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Ruihan-Yintannergooding
Ruihan-Yin
and
tannergooding
authored
Update the CPUID and XSAVE logics for APX (#104637)
* Add APX doc. * script-gen changes. * XSTATE changes * hand-written CPUID check part * fix * Fix merge error. * bug fixes * Bug fix * bug fix * resolve commnets. * re-generate the ISA changes to propagate the changes in ThunkGenerator. * resolve comments * use byte code for EGPR XSAVE logics. * resolve comments. --------- Co-authored-by: Tanner Gooding <[email protected]>
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-131
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21 files changed

+460
-131
lines changed

‎src/coreclr/System.Private.CoreLib/src/System/Runtime/ExceptionServices/AsmOffsets.cs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,9 @@ class AsmOffsets
1616
// Debug build offsets
1717
#if TARGET_AMD64
1818
#if TARGET_UNIX
19-
public const int SIZEOF__REGDISPLAY = 0x1a90;
20-
public const int OFFSETOF__REGDISPLAY__SP = 0x1a78;
21-
public const int OFFSETOF__REGDISPLAY__ControlPC = 0x1a80;
19+
public const int SIZEOF__REGDISPLAY = 0x1b90;
20+
public const int OFFSETOF__REGDISPLAY__SP = 0x1b78;
21+
public const int OFFSETOF__REGDISPLAY__ControlPC = 0x1b80;
2222
#else // TARGET_UNIX
2323
public const int SIZEOF__REGDISPLAY = 0xbf0;
2424
public const int OFFSETOF__REGDISPLAY__SP = 0xbd8;
@@ -68,9 +68,9 @@ class AsmOffsets
6868
// Release build offsets
6969
#if TARGET_AMD64
7070
#if TARGET_UNIX
71-
public const int SIZEOF__REGDISPLAY = 0x1a80;
72-
public const int OFFSETOF__REGDISPLAY__SP = 0x1a70;
73-
public const int OFFSETOF__REGDISPLAY__ControlPC = 0x1a78;
71+
public const int SIZEOF__REGDISPLAY = 0x1b80;
72+
public const int OFFSETOF__REGDISPLAY__SP = 0x1b70;
73+
public const int OFFSETOF__REGDISPLAY__ControlPC = 0x1b78;
7474
#else // TARGET_UNIX
7575
public const int SIZEOF__REGDISPLAY = 0xbf0;
7676
public const int OFFSETOF__REGDISPLAY__SP = 0xbd0;
@@ -120,7 +120,7 @@ class AsmOffsets
120120

121121
#if TARGET_AMD64
122122
#if TARGET_UNIX
123-
public const int SIZEOF__PAL_LIMITED_CONTEXT = 0xc20;
123+
public const int SIZEOF__PAL_LIMITED_CONTEXT = 0xca0;
124124
#else // TARGET_UNIX
125125
public const int SIZEOF__PAL_LIMITED_CONTEXT = 0x4d0;
126126
#endif // TARGET_UNIX

‎src/coreclr/inc/corinfoinstructionset.h

Lines changed: 72 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -81,33 +81,35 @@ enum CORINFO_InstructionSet
8181
InstructionSet_VectorT128=36,
8282
InstructionSet_VectorT256=37,
8383
InstructionSet_VectorT512=38,
84-
InstructionSet_X86Base_X64=39,
85-
InstructionSet_SSE_X64=40,
86-
InstructionSet_SSE2_X64=41,
87-
InstructionSet_SSE3_X64=42,
88-
InstructionSet_SSSE3_X64=43,
89-
InstructionSet_SSE41_X64=44,
90-
InstructionSet_SSE42_X64=45,
91-
InstructionSet_AVX_X64=46,
92-
InstructionSet_AVX2_X64=47,
93-
InstructionSet_AES_X64=48,
94-
InstructionSet_BMI1_X64=49,
95-
InstructionSet_BMI2_X64=50,
96-
InstructionSet_FMA_X64=51,
97-
InstructionSet_LZCNT_X64=52,
98-
InstructionSet_PCLMULQDQ_X64=53,
99-
InstructionSet_POPCNT_X64=54,
100-
InstructionSet_AVXVNNI_X64=55,
101-
InstructionSet_MOVBE_X64=56,
102-
InstructionSet_X86Serialize_X64=57,
103-
InstructionSet_EVEX_X64=58,
104-
InstructionSet_AVX512F_X64=59,
105-
InstructionSet_AVX512BW_X64=60,
106-
InstructionSet_AVX512CD_X64=61,
107-
InstructionSet_AVX512DQ_X64=62,
108-
InstructionSet_AVX512VBMI_X64=63,
109-
InstructionSet_AVX10v1_X64=64,
110-
InstructionSet_AVX10v1_V512_X64=65,
84+
InstructionSet_APX=39,
85+
InstructionSet_X86Base_X64=40,
86+
InstructionSet_SSE_X64=41,
87+
InstructionSet_SSE2_X64=42,
88+
InstructionSet_SSE3_X64=43,
89+
InstructionSet_SSSE3_X64=44,
90+
InstructionSet_SSE41_X64=45,
91+
InstructionSet_SSE42_X64=46,
92+
InstructionSet_AVX_X64=47,
93+
InstructionSet_AVX2_X64=48,
94+
InstructionSet_AES_X64=49,
95+
InstructionSet_BMI1_X64=50,
96+
InstructionSet_BMI2_X64=51,
97+
InstructionSet_FMA_X64=52,
98+
InstructionSet_LZCNT_X64=53,
99+
InstructionSet_PCLMULQDQ_X64=54,
100+
InstructionSet_POPCNT_X64=55,
101+
InstructionSet_AVXVNNI_X64=56,
102+
InstructionSet_MOVBE_X64=57,
103+
InstructionSet_X86Serialize_X64=58,
104+
InstructionSet_EVEX_X64=59,
105+
InstructionSet_AVX512F_X64=60,
106+
InstructionSet_AVX512BW_X64=61,
107+
InstructionSet_AVX512CD_X64=62,
108+
InstructionSet_AVX512DQ_X64=63,
109+
InstructionSet_AVX512VBMI_X64=64,
110+
InstructionSet_AVX10v1_X64=65,
111+
InstructionSet_AVX10v1_V512_X64=66,
112+
InstructionSet_APX_X64=67,
111113
#endif // TARGET_AMD64
112114
#ifdef TARGET_X86
113115
InstructionSet_X86Base=1,
@@ -148,33 +150,35 @@ enum CORINFO_InstructionSet
148150
InstructionSet_VectorT128=36,
149151
InstructionSet_VectorT256=37,
150152
InstructionSet_VectorT512=38,
151-
InstructionSet_X86Base_X64=39,
152-
InstructionSet_SSE_X64=40,
153-
InstructionSet_SSE2_X64=41,
154-
InstructionSet_SSE3_X64=42,
155-
InstructionSet_SSSE3_X64=43,
156-
InstructionSet_SSE41_X64=44,
157-
InstructionSet_SSE42_X64=45,
158-
InstructionSet_AVX_X64=46,
159-
InstructionSet_AVX2_X64=47,
160-
InstructionSet_AES_X64=48,
161-
InstructionSet_BMI1_X64=49,
162-
InstructionSet_BMI2_X64=50,
163-
InstructionSet_FMA_X64=51,
164-
InstructionSet_LZCNT_X64=52,
165-
InstructionSet_PCLMULQDQ_X64=53,
166-
InstructionSet_POPCNT_X64=54,
167-
InstructionSet_AVXVNNI_X64=55,
168-
InstructionSet_MOVBE_X64=56,
169-
InstructionSet_X86Serialize_X64=57,
170-
InstructionSet_EVEX_X64=58,
171-
InstructionSet_AVX512F_X64=59,
172-
InstructionSet_AVX512BW_X64=60,
173-
InstructionSet_AVX512CD_X64=61,
174-
InstructionSet_AVX512DQ_X64=62,
175-
InstructionSet_AVX512VBMI_X64=63,
176-
InstructionSet_AVX10v1_X64=64,
177-
InstructionSet_AVX10v1_V512_X64=65,
153+
InstructionSet_APX=39,
154+
InstructionSet_X86Base_X64=40,
155+
InstructionSet_SSE_X64=41,
156+
InstructionSet_SSE2_X64=42,
157+
InstructionSet_SSE3_X64=43,
158+
InstructionSet_SSSE3_X64=44,
159+
InstructionSet_SSE41_X64=45,
160+
InstructionSet_SSE42_X64=46,
161+
InstructionSet_AVX_X64=47,
162+
InstructionSet_AVX2_X64=48,
163+
InstructionSet_AES_X64=49,
164+
InstructionSet_BMI1_X64=50,
165+
InstructionSet_BMI2_X64=51,
166+
InstructionSet_FMA_X64=52,
167+
InstructionSet_LZCNT_X64=53,
168+
InstructionSet_PCLMULQDQ_X64=54,
169+
InstructionSet_POPCNT_X64=55,
170+
InstructionSet_AVXVNNI_X64=56,
171+
InstructionSet_MOVBE_X64=57,
172+
InstructionSet_X86Serialize_X64=58,
173+
InstructionSet_EVEX_X64=59,
174+
InstructionSet_AVX512F_X64=60,
175+
InstructionSet_AVX512BW_X64=61,
176+
InstructionSet_AVX512CD_X64=62,
177+
InstructionSet_AVX512DQ_X64=63,
178+
InstructionSet_AVX512VBMI_X64=64,
179+
InstructionSet_AVX10v1_X64=65,
180+
InstructionSet_AVX10v1_V512_X64=66,
181+
InstructionSet_APX_X64=67,
178182
#endif // TARGET_X86
179183

180184
};
@@ -344,6 +348,8 @@ struct CORINFO_InstructionSetFlags
344348
AddInstructionSet(InstructionSet_AVX10v1_X64);
345349
if (HasInstructionSet(InstructionSet_AVX10v1_V512))
346350
AddInstructionSet(InstructionSet_AVX10v1_V512_X64);
351+
if (HasInstructionSet(InstructionSet_APX))
352+
AddInstructionSet(InstructionSet_APX_X64);
347353
#endif // TARGET_AMD64
348354
#ifdef TARGET_X86
349355
#endif // TARGET_X86
@@ -532,6 +538,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
532538
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
533539
if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
534540
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512_X64);
541+
if (resultflags.HasInstructionSet(InstructionSet_APX) && !resultflags.HasInstructionSet(InstructionSet_APX_X64))
542+
resultflags.RemoveInstructionSet(InstructionSet_APX);
543+
if (resultflags.HasInstructionSet(InstructionSet_APX_X64) && !resultflags.HasInstructionSet(InstructionSet_APX))
544+
resultflags.RemoveInstructionSet(InstructionSet_APX_X64);
535545
if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
536546
resultflags.RemoveInstructionSet(InstructionSet_SSE);
537547
if (resultflags.HasInstructionSet(InstructionSet_SSE2) && !resultflags.HasInstructionSet(InstructionSet_SSE))
@@ -940,6 +950,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
940950
return "VectorT256";
941951
case InstructionSet_VectorT512 :
942952
return "VectorT512";
953+
case InstructionSet_APX :
954+
return "APX";
955+
case InstructionSet_APX_X64 :
956+
return "APX_X64";
943957
#endif // TARGET_AMD64
944958
#ifdef TARGET_X86
945959
case InstructionSet_X86Base :
@@ -1018,6 +1032,8 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
10181032
return "VectorT256";
10191033
case InstructionSet_VectorT512 :
10201034
return "VectorT512";
1035+
case InstructionSet_APX :
1036+
return "APX";
10211037
#endif // TARGET_X86
10221038

10231039
default:
@@ -1088,6 +1104,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
10881104
case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128;
10891105
case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256;
10901106
case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512;
1107+
case READYTORUN_INSTRUCTION_Apx: return InstructionSet_APX;
10911108
#endif // TARGET_AMD64
10921109
#ifdef TARGET_X86
10931110
case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;
@@ -1125,6 +1142,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
11251142
case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128;
11261143
case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256;
11271144
case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512;
1145+
case READYTORUN_INSTRUCTION_Apx: return InstructionSet_APX;
11281146
#endif // TARGET_X86
11291147

11301148
default:

‎src/coreclr/inc/jiteeversionguid.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -43,11 +43,11 @@ typedef const GUID *LPCGUID;
4343
#define GUID_DEFINED
4444
#endif // !GUID_DEFINED
4545

46-
constexpr GUID JITEEVersionIdentifier = { /* 6f498741-c4a2-4863-9dd7-06ad7d788443 */
47-
0x6f498741,
48-
0xc4a2,
49-
0x4863,
50-
{0x9d, 0xd7, 0x06, 0xad, 0x7d, 0x78, 0x84, 0x43}
46+
constexpr GUID JITEEVersionIdentifier = { /* 381fc250-b8f3-4cee-834e-b0bc682a09f2 */
47+
0x381fc250,
48+
0xb8f3,
49+
0x4cee,
50+
{0x83, 0x4e, 0xb0, 0xbc, 0x68, 0x2a, 0x09, 0xf2}
5151
};
5252

5353
//////////////////////////////////////////////////////////////////////////////////////////////////////////

‎src/coreclr/inc/readytoruninstructionset.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ enum ReadyToRunInstructionSet
5555
READYTORUN_INSTRUCTION_Avx10v1=44,
5656
READYTORUN_INSTRUCTION_Avx10v1_V512=46,
5757
READYTORUN_INSTRUCTION_EVEX=47,
58+
READYTORUN_INSTRUCTION_Apx=48,
5859

5960
};
6061

‎src/coreclr/jit/hwintrinsic.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -804,6 +804,7 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
804804
{ NI_Illegal, NI_Illegal }, // VectorT128
805805
{ NI_Illegal, NI_Illegal }, // VectorT256
806806
{ NI_Illegal, NI_Illegal }, // VectorT512
807+
{ NI_Illegal, NI_Illegal }, // APX
807808
{ FIRST_NI_X86Base_X64, LAST_NI_X86Base_X64 },
808809
{ FIRST_NI_SSE_X64, LAST_NI_SSE_X64 },
809810
{ FIRST_NI_SSE2_X64, LAST_NI_SSE2_X64 },

‎src/coreclr/nativeaot/Runtime/windows/PalRedhawkMinWin.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,10 @@
3737
#define REDHAWK_PALEXPORT extern "C"
3838
#define REDHAWK_PALAPI __stdcall
3939

40+
#ifndef XSTATE_MASK_APX
41+
#define XSTATE_MASK_APX (0x80000)
42+
#endif // XSTATE_MASK_APX
43+
4044
// Index for the fiber local storage of the attached thread pointer
4145
static uint32_t g_flsIndex = FLS_OUT_OF_INDEXES;
4246

@@ -541,7 +545,7 @@ REDHAWK_PALEXPORT CONTEXT* PalAllocateCompleteOSContext(_Out_ uint8_t** contextB
541545
#endif //TARGET_X86
542546

543547
#if defined(TARGET_X86) || defined(TARGET_AMD64)
544-
const DWORD64 xStateFeatureMask = XSTATE_MASK_AVX | XSTATE_MASK_AVX512;
548+
const DWORD64 xStateFeatureMask = XSTATE_MASK_AVX | XSTATE_MASK_AVX512 | XSTATE_MASK_APX;
545549
const ULONG64 xStateCompactionMask = XSTATE_MASK_LEGACY | XSTATE_MASK_MPX | xStateFeatureMask;
546550
#elif defined(TARGET_ARM64)
547551
const DWORD64 xStateFeatureMask = XSTATE_MASK_ARM64_SVE;
@@ -632,9 +636,9 @@ REDHAWK_PALEXPORT _Success_(return) bool REDHAWK_PALAPI PalGetCompleteThreadCont
632636
// This should not normally fail.
633637
// The system silently ignores any feature specified in the FeatureMask which is not enabled on the processor.
634638
#if defined(TARGET_X86) || defined(TARGET_AMD64)
635-
if (!SetXStateFeaturesMask(pCtx, XSTATE_MASK_AVX | XSTATE_MASK_AVX512))
639+
if (!SetXStateFeaturesMask(pCtx, XSTATE_MASK_AVX | XSTATE_MASK_AVX512 | XSTATE_MASK_APX))
636640
{
637-
_ASSERTE(!"Could not apply XSTATE_MASK_AVX | XSTATE_MASK_AVX512");
641+
_ASSERTE(!"Could not apply XSTATE_MASK_AVX | XSTATE_MASK_AVX512 | XSTATE_MASK_APX");
638642
return FALSE;
639643
}
640644
#elif defined(TARGET_ARM64)

‎src/coreclr/pal/inc/pal.h

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1374,12 +1374,14 @@ typedef struct _KNONVOLATILE_CONTEXT_POINTERS {
13741374
#define XSTATE_AVX512_KMASK (5)
13751375
#define XSTATE_AVX512_ZMM_H (6)
13761376
#define XSTATE_AVX512_ZMM (7)
1377+
#define XSTATE_APX (19)
13771378

13781379
#define XSTATE_MASK_GSSE (UI64(1) << (XSTATE_GSSE))
13791380
#define XSTATE_MASK_AVX (XSTATE_MASK_GSSE)
13801381
#define XSTATE_MASK_AVX512 ((UI64(1) << (XSTATE_AVX512_KMASK)) | \
13811382
(UI64(1) << (XSTATE_AVX512_ZMM_H)) | \
13821383
(UI64(1) << (XSTATE_AVX512_ZMM)))
1384+
#define XSTATE_MASK_APX (UI64(1) << (XSTATE_APX))
13831385

13841386
typedef struct DECLSPEC_ALIGN(16) _M128A {
13851387
ULONGLONG Low;
@@ -1616,6 +1618,27 @@ typedef struct DECLSPEC_ALIGN(16) _CONTEXT {
16161618
M512 Zmm30;
16171619
M512 Zmm31;
16181620
};
1621+
1622+
struct
1623+
{
1624+
DWORD64 Egpr16;
1625+
DWORD64 Egpr17;
1626+
DWORD64 Egpr18;
1627+
DWORD64 Egpr19;
1628+
DWORD64 Egpr20;
1629+
DWORD64 Egpr21;
1630+
DWORD64 Egpr22;
1631+
DWORD64 Egpr23;
1632+
DWORD64 Egpr24;
1633+
DWORD64 Egpr25;
1634+
DWORD64 Egpr26;
1635+
DWORD64 Egpr27;
1636+
DWORD64 Egpr28;
1637+
DWORD64 Egpr29;
1638+
DWORD64 Egpr30;
1639+
DWORD64 Egpr31;
1640+
};
1641+
16191642
} CONTEXT, *PCONTEXT, *LPCONTEXT;
16201643

16211644
//

‎src/coreclr/pal/src/arch/amd64/asmconstants.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,12 +8,14 @@
88
#define XSTATE_AVX512_KMASK (5)
99
#define XSTATE_AVX512_ZMM_H (6)
1010
#define XSTATE_AVX512_ZMM (7)
11+
#define XSTATE_APX (19)
1112

1213
#define XSTATE_MASK_GSSE (1 << (XSTATE_GSSE))
1314
#define XSTATE_MASK_AVX (XSTATE_MASK_GSSE)
1415
#define XSTATE_MASK_AVX512 ((1 << (XSTATE_AVX512_KMASK)) | \
1516
(1 << (XSTATE_AVX512_ZMM_H)) | \
1617
(1 << (XSTATE_AVX512_ZMM)))
18+
#define XSTATE_MASK_APX (1 << (XSTATE_APX))
1719

1820
// The arch bit is normally set in the flag constants below. Since this is already arch-specific code and the arch bit is not
1921
// relevant, the arch bit is excluded from the flag constants below for simpler tests.
@@ -91,7 +93,8 @@
9193
#define CONTEXT_KMask0 CONTEXT_Ymm0H+(16*16)
9294
#define CONTEXT_Zmm0H CONTEXT_KMask0+(8*8)
9395
#define CONTEXT_Zmm16 CONTEXT_Zmm0H+(32*16)
94-
#define CONTEXT_Size CONTEXT_Zmm16+(64*16)
96+
#define CONTEXT_Egpr CONTEXT_Zmm16+(64*16)
97+
#define CONTEXT_Size CONTEXT_Egpr+(8*16)
9598

9699
#else // HOST_64BIT
97100

‎src/coreclr/pal/src/arch/amd64/context2.S

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,46 @@ LOCAL_LABEL(Done_Restore_CONTEXT_FLOATING_POINT):
183183
kmovq k6, qword ptr [rdi + (CONTEXT_KMask0 + 6 * 8)]
184184
kmovq k7, qword ptr [rdi + (CONTEXT_KMask0 + 7 * 8)]
185185

186+
test BYTE PTR [rdi + CONTEXT_XStateFeaturesMask], XSTATE_MASK_APX
187+
je LOCAL_LABEL(Done_Restore_CONTEXT_XSTATE)
188+
189+
// TODO-XArch-APX:
190+
// we are using raw hex code here to emit EGPRs-related changes,
191+
// we will need to come back and re-write this part when assembler supports EGPRs.
192+
193+
// mov r16, qword ptr [rdi + CONTEXT_Egpr + 0 * 8]
194+
.byte 0xd5, 0x48, 0x8b, 0x87, 0x20, 0x0c, 0x00, 0x00
195+
// mov r17, qword ptr [rdi + CONTEXT_Egpr + 1 * 8]
196+
.byte 0xd5, 0x48, 0x8b, 0x8f, 0x28, 0x0c, 0x00, 0x00
197+
// mov r18, qword ptr [rdi + CONTEXT_Egpr + 2 * 8]
198+
.byte 0xd5, 0x48, 0x8b, 0x97, 0x30, 0x0c, 0x00, 0x00
199+
// mov r19, qword ptr [rdi + CONTEXT_Egpr + 3 * 8]
200+
.byte 0xd5, 0x48, 0x8b, 0x9f, 0x38, 0x0c, 0x00, 0x00
201+
// mov r20, qword ptr [rdi + CONTEXT_Egpr + 4 * 8]
202+
.byte 0xd5, 0x48, 0x8b, 0xa7, 0x40, 0x0c, 0x00, 0x00
203+
// mov r21, qword ptr [rdi + CONTEXT_Egpr + 5 * 8]
204+
.byte 0xd5, 0x48, 0x8b, 0xaf, 0x48, 0x0c, 0x00, 0x00
205+
// mov r22, qword ptr [rdi + CONTEXT_Egpr + 6 * 8]
206+
.byte 0xd5, 0x48, 0x8b, 0xb7, 0x50, 0x0c, 0x00, 0x00
207+
// mov r23, qword ptr [rdi + CONTEXT_Egpr + 7 * 8]
208+
.byte 0xd5, 0x48, 0x8b, 0xbf, 0x58, 0x0c, 0x00, 0x00
209+
// mov r24, qword ptr [rdi + CONTEXT_Egpr + 8 * 8]
210+
.byte 0xd5, 0x4c, 0x8b, 0x87, 0x60, 0x0c, 0x00, 0x00
211+
// mov r25, qword ptr [rdi + CONTEXT_Egpr + 9 * 8]
212+
.byte 0xd5, 0x4c, 0x8b, 0x8f, 0x68, 0x0c, 0x00, 0x00
213+
// mov r26, qword ptr [rdi + CONTEXT_Egpr + 10 * 8]
214+
.byte 0xd5, 0x4c, 0x8b, 0x97, 0x70, 0x0c, 0x00, 0x00
215+
// mov r27, qword ptr [rdi + CONTEXT_Egpr + 11 * 8]
216+
.byte 0xd5, 0x4c, 0x8b, 0x9f, 0x78, 0x0c, 0x00, 0x00
217+
// mov r28, qword ptr [rdi + CONTEXT_Egpr + 12 * 8]
218+
.byte 0xd5, 0x4c, 0x8b, 0xa7, 0x80, 0x0c, 0x00, 0x00
219+
// mov r29, qword ptr [rdi + CONTEXT_Egpr + 13 * 8]
220+
.byte 0xd5, 0x4c, 0x8b, 0xaf, 0x88, 0x0c, 0x00, 0x00
221+
// mov r30, qword ptr [rdi + CONTEXT_Egpr + 14 * 8]
222+
.byte 0xd5, 0x4c, 0x8b, 0xb7, 0x90, 0x0c, 0x00, 0x00
223+
// mov r31, qword ptr [rdi + CONTEXT_Egpr + 15 * 8]
224+
.byte 0xd5, 0x4c, 0x8b, 0xbf, 0x98, 0x0c, 0x00, 0x00
225+
186226
LOCAL_LABEL(Done_Restore_CONTEXT_XSTATE):
187227

188228
test BYTE PTR [rdi + CONTEXT_ContextFlags], CONTEXT_CONTROL

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