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r30shahr30shah
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Merge pull request #19926 from zl-wang/master
Change to use isOffheapAllocationEnabled query
2 parents d98e1e5 + 8e7895f commit c5b3b09

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5 files changed

+17
-17
lines changed

5 files changed

+17
-17
lines changed

‎runtime/compiler/aarch64/codegen/J9TreeEvaluator.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3458,7 +3458,7 @@ J9::ARM64::TreeEvaluator::VMnewEvaluator(TR::Node *node, TR::CodeGenerator *cg)
34583458
genInitArrayHeader(node, cg, clazz, resultReg, classReg, lengthReg, zeroReg, tempReg1, isBatchClearTLHEnabled, tlhHasNotBeenCleared);
34593459

34603460
#ifdef J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION
3461-
if (TR::Compiler->om.isIndexableDataAddrPresent())
3461+
if (TR::Compiler->om.isOffHeapAllocationEnabled())
34623462
{
34633463
/* Here we'll update dataAddr slot for both fixed and variable length arrays. Fixed length arrays are
34643464
* simple as we just need to check first child of the node for array size. For variable length arrays,

‎runtime/compiler/env/VMJ9.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4084,7 +4084,7 @@ TR_J9VMBase::initializeLocalArrayHeader(TR::Compilation * comp, TR::Node * alloc
40844084
prevTree = TR::TreeTop::create(comp, prevTree, node);
40854085

40864086
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
4087-
if (TR::Compiler->om.isIndexableDataAddrPresent())
4087+
if (TR::Compiler->om.isOffHeapAllocationEnabled())
40884088
{
40894089
// -----------------------------------------------------------------------------------
40904090
// Initialize data address field

‎runtime/compiler/p/codegen/J9TreeEvaluator.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6483,7 +6483,7 @@ TR::Register *J9::Power::TreeEvaluator::VMnewEvaluator(TR::Node *node, TR::CodeG
64836483
tmp5Reg, tmp4Reg, conditions, needZeroInit, cg);
64846484

64856485
#ifdef J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION
6486-
if (TR::Compiler->om.isIndexableDataAddrPresent())
6486+
if (TR::Compiler->om.isOffHeapAllocationEnabled())
64876487
{
64886488
/* Here we'll update dataAddr slot for both fixed and variable length arrays. Fixed length arrays are
64896489
* simple as we just need to check first child of the node for array size. For variable length arrays,

‎runtime/compiler/x/codegen/J9TreeEvaluator.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1500,8 +1500,8 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
15001500
TR::LabelSymbol *loopLabel = generateLabelSymbol(cg);
15011501
TR::LabelSymbol *nonZeroFirstDimLabel = generateLabelSymbol(cg);
15021502
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
1503-
bool isIndexableDataAddrPresent = TR::Compiler->om.isIndexableDataAddrPresent();
1504-
TR::LabelSymbol *populateFirstDimDataAddrSlot = isIndexableDataAddrPresent ? generateLabelSymbol(cg) : NULL;
1503+
bool isOffHeapAllocationEnabled = TR::Compiler->om.isOffHeapAllocationEnabled();
1504+
TR::LabelSymbol *populateFirstDimDataAddrSlot = isOffHeapAllocationEnabled? generateLabelSymbol(cg) : NULL;
15051505
#endif /* defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION) */
15061506

15071507
startLabel->setStartInternalControlFlow();
@@ -1558,7 +1558,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
15581558
generateMemImmInstruction(TR::InstOpCode::S4MemImm4, node, generateX86MemoryReference(targetReg, fej9->getOffsetOfDiscontiguousArraySizeField(), cg), 0, cg);
15591559

15601560
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
1561-
if (isIndexableDataAddrPresent)
1561+
if (isOffHeapAllocationEnabled)
15621562
{
15631563
// Load dataAddr slot offset difference since 0 size arrays are treated as discontiguous.
15641564
TR_ASSERT_FATAL_WITH_NODE(node,
@@ -1651,7 +1651,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
16511651
generateMemImmInstruction(TR::InstOpCode::S4MemImm4, node, generateX86MemoryReference(temp2Reg, fej9->getOffsetOfDiscontiguousArraySizeField(), cg), 0, cg);
16521652

16531653
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
1654-
if (isIndexableDataAddrPresent)
1654+
if (isOffHeapAllocationEnabled)
16551655
{
16561656
// Populate dataAddr slot for 2nd dimension zero size array.
16571657
generateRegMemInstruction(TR::InstOpCode::LEARegMem(),
@@ -1691,7 +1691,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
16911691
generateLabelInstruction(TR::InstOpCode::JA4, node, loopLabel, cg);
16921692

16931693
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
1694-
if (isIndexableDataAddrPresent)
1694+
if (isOffHeapAllocationEnabled)
16951695
{
16961696
// No offset is needed since 1st dimension array is contiguous.
16971697
generateRegRegInstruction(TR::InstOpCode::XOR4RegReg, node, temp3Reg, temp3Reg, cg);
@@ -1749,7 +1749,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
17491749
generateLabelInstruction(TR::InstOpCode::JMP4, node, oolFailLabel, cg);
17501750

17511751
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
1752-
if (isIndexableDataAddrPresent)
1752+
if (isOffHeapAllocationEnabled)
17531753
{
17541754
/* Populate dataAddr slot of 1st dimension array. Arrays of non-zero size
17551755
* use contiguous header layout while zero size arrays use discontiguous header layout.
@@ -8119,7 +8119,7 @@ J9::X86::TreeEvaluator::VMnewEvaluator(
81198119
}
81208120

81218121
#ifdef J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION
8122-
if (isArrayNew && TR::Compiler->om.isIndexableDataAddrPresent())
8122+
if (isArrayNew && TR::Compiler->om.isOffHeapAllocationEnabled())
81238123
{
81248124
handleOffHeapDataForArrays(node, sizeReg, targetReg, tempReg, srm, cg);
81258125
}

‎runtime/compiler/z/codegen/J9TreeEvaluator.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4770,8 +4770,8 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
47704770
TR::LabelSymbol *oolFailLabel = generateLabelSymbol(cg);
47714771

47724772
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
4773-
bool isIndexableDataAddrPresent = TR::Compiler->om.isIndexableDataAddrPresent();
4774-
TR::LabelSymbol *populateFirstDimDataAddrSlot = isIndexableDataAddrPresent ? generateLabelSymbol(cg) : NULL;
4773+
bool isOffHeapAllocationEnabled = TR::Compiler->om.isOffHeapAllocationEnabled();
4774+
TR::LabelSymbol *populateFirstDimDataAddrSlot = isOffHeapAllocationEnabled ? generateLabelSymbol(cg) : NULL;
47754775
#endif /* defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION) */
47764776

47774777
// oolJumpLabel is a common point that all branches will jump to. From this label, we branch to OOL code.
@@ -4851,7 +4851,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
48514851
}
48524852

48534853
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
4854-
if (isIndexableDataAddrPresent)
4854+
if (isOffHeapAllocationEnabled)
48554855
{
48564856
TR_ASSERT_FATAL_WITH_NODE(node,
48574857
(TR::Compiler->om.compressObjectReferences()
@@ -4961,7 +4961,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
49614961
TR::Register *temp3Reg = cg->allocateRegister();
49624962

49634963
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
4964-
if (isIndexableDataAddrPresent)
4964+
if (isOffHeapAllocationEnabled)
49654965
{
49664966
// Populate dataAddr slot for 2nd dimension zero size array.
49674967
generateRXInstruction(cg,
@@ -5001,7 +5001,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
50015001
generateS390CompareAndBranchInstruction(cg, TR::InstOpCode::CL, node, firstDimLenReg, 0, TR::InstOpCode::COND_BNE, loopLabel, false);
50025002

50035003
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
5004-
if (isIndexableDataAddrPresent)
5004+
if (isOffHeapAllocationEnabled)
50055005
{
50065006
// No offset is needed since 1st dimension array is contiguous.
50075007
generateRRInstruction(cg, TR::InstOpCode::getXORRegOpCode(), node, temp1Reg, temp1Reg);
@@ -5029,7 +5029,7 @@ static TR::Register * generateMultianewArrayWithInlineAllocators(TR::Node *node,
50295029
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BRC, node, oolFailLabel);
50305030

50315031
#if defined(J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION)
5032-
if (isIndexableDataAddrPresent)
5032+
if (isOffHeapAllocationEnabled)
50335033
{
50345034
/* Populate dataAddr slot of 1st dimension array. Arrays of non-zero size
50355035
* use contiguous header layout while zero size arrays use discontiguous header layout.
@@ -11015,7 +11015,7 @@ J9::Z::TreeEvaluator::VMnewEvaluator(TR::Node * node, TR::CodeGenerator * cg)
1101511015
resReg, enumReg, dataSizeReg, litPoolBaseReg, conditions, cg);
1101611016

1101711017
#ifdef J9VM_GC_ENABLE_SPARSE_HEAP_ALLOCATION
11018-
if (TR::Compiler->om.isIndexableDataAddrPresent())
11018+
if (TR::Compiler->om.isOffHeapAllocationEnabled())
1101911019
{
1102011020
/* Here we'll update dataAddr slot for both fixed and variable length arrays. Fixed length arrays are
1102111021
* simple as we just need to check first child of the node for array size. For variable length arrays

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