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Merge pull request #2402 from Okarss/master
[STM32 FSDEV] Fix ISR race conditions
2 parents 5002ce8 + 2d3d148 commit 71ce4b8

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2 files changed

+56
-52
lines changed

2 files changed

+56
-52
lines changed

src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -128,16 +128,16 @@
128128
# define DCD_STM32_BTABLE_BASE 0U
129129
#endif
130130

131-
#ifndef DCD_STM32_BTABLE_LENGTH
132-
# define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE)
131+
#ifndef DCD_STM32_BTABLE_SIZE
132+
# define DCD_STM32_BTABLE_SIZE (FSDEV_PMA_SIZE - DCD_STM32_BTABLE_BASE)
133133
#endif
134134

135135
/***************************************************
136136
* Checks, structs, defines, function definitions, etc.
137137
*/
138138

139139
TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
140-
TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH), "BTABLE does not fit in PMA RAM");
140+
TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_SIZE)) <= (FSDEV_PMA_SIZE), "BTABLE does not fit in PMA RAM");
141141
TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
142142

143143
//--------------------------------------------------------------------+
@@ -559,7 +559,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
559559
// Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
560560
pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
561561
pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
562-
#ifdef PMA_32BIT_ACCESS
562+
#ifdef FSDEV_BUS_32BIT
563563
dcd_event_setup_received(0, (uint8_t*)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true);
564564
#else
565565
// The setup_received function uses memcpy, so this must first copy the setup data into
@@ -673,13 +673,13 @@ void dcd_int_handler(uint8_t rhport) {
673673

674674
/* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
675675
if(int_status & USB_ISTR_SOF) {
676-
USB->ISTR &=~USB_ISTR_SOF;
676+
USB->ISTR = (fsdev_bus_t)~USB_ISTR_SOF;
677677
dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
678678
}
679679

680680
if(int_status & USB_ISTR_RESET) {
681681
// USBRST is start of reset.
682-
USB->ISTR &=~USB_ISTR_RESET;
682+
USB->ISTR = (fsdev_bus_t)~USB_ISTR_RESET;
683683
dcd_handle_bus_reset();
684684
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
685685
return; // Don't do the rest of the things here; perhaps they've been cleared?
@@ -697,7 +697,7 @@ void dcd_int_handler(uint8_t rhport) {
697697
USB->CNTR &= ~USB_CNTR_LPMODE;
698698
USB->CNTR &= ~USB_CNTR_FSUSP;
699699

700-
USB->ISTR &=~USB_ISTR_WKUP;
700+
USB->ISTR = (fsdev_bus_t)~USB_ISTR_WKUP;
701701
dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
702702
}
703703

@@ -711,7 +711,7 @@ void dcd_int_handler(uint8_t rhport) {
711711
USB->CNTR |= USB_CNTR_LPMODE;
712712

713713
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
714-
USB->ISTR &=~USB_ISTR_SUSP;
714+
USB->ISTR = (fsdev_bus_t)~USB_ISTR_SUSP;
715715
dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
716716
}
717717

@@ -724,7 +724,7 @@ void dcd_int_handler(uint8_t rhport) {
724724
{
725725
remoteWakeCountdown--;
726726
}
727-
USB->ISTR &=~USB_ISTR_ESOF;
727+
USB->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF;
728728
}
729729
}
730730

@@ -786,7 +786,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
786786
}
787787

788788
// Ensure allocated buffer is aligned
789-
#ifdef PMA_32BIT_ACCESS
789+
#ifdef FSDEV_BUS_32BIT
790790
length = (length + 3) & ~0x03;
791791
#else
792792
length = (length + 1) & ~0x01;
@@ -798,7 +798,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
798798
ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
799799

800800
// Verify no overflow
801-
TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF);
801+
TU_ASSERT(ep_buf_ptr <= FSDEV_PMA_SIZE, 0xFFFF);
802802

803803
epXferCtl->pma_ptr = addr;
804804
epXferCtl->pma_alloc_size = length;
@@ -1227,7 +1227,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
12271227
}
12281228
}
12291229

1230-
#ifdef PMA_32BIT_ACCESS
1230+
#ifdef FSDEV_BUS_32BIT
12311231
static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
12321232
{
12331233
const uint8_t* srcVal = src;
@@ -1283,15 +1283,15 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
12831283
__IO uint16_t *pdwVal;
12841284

12851285
srcVal = src;
1286-
pdwVal = &pma[PMA_STRIDE*(dst>>1)];
1286+
pdwVal = &pma[FSDEV_PMA_STRIDE * (dst >> 1)];
12871287

12881288
while (n--)
12891289
{
12901290
temp1 = (uint16_t)*srcVal;
12911291
srcVal++;
12921292
temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U)) ;
12931293
*pdwVal = temp2;
1294-
pdwVal += PMA_STRIDE;
1294+
pdwVal += FSDEV_PMA_STRIDE;
12951295
srcVal++;
12961296
}
12971297

@@ -1323,7 +1323,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
13231323
// We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
13241324
// last lin byte will be combined with wrapped part
13251325
// To ensure PMA is always access aligned (dst aligned to 16 or 32 bit)
1326-
#ifdef PMA_32BIT_ACCESS
1326+
#ifdef FSDEV_BUS_32BIT
13271327
if((cnt_lin & 0x03) && cnt_wrap)
13281328
{
13291329
// Copy first linear part
@@ -1386,7 +1386,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
13861386
return true;
13871387
}
13881388

1389-
#ifdef PMA_32BIT_ACCESS
1389+
#ifdef FSDEV_BUS_32BIT
13901390
static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
13911391
{
13921392
uint8_t* dstVal = dst;
@@ -1434,21 +1434,21 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
14341434
__IO const uint16_t *pdwVal;
14351435
uint32_t temp;
14361436

1437-
pdwVal = &pma[PMA_STRIDE*(src>>1)];
1437+
pdwVal = &pma[FSDEV_PMA_STRIDE * (src >> 1)];
14381438
uint8_t *dstVal = (uint8_t*)dst;
14391439

14401440
while (n--)
14411441
{
14421442
temp = *pdwVal;
1443-
pdwVal += PMA_STRIDE;
1443+
pdwVal += FSDEV_PMA_STRIDE;
14441444
*dstVal++ = ((temp >> 0) & 0xFF);
14451445
*dstVal++ = ((temp >> 8) & 0xFF);
14461446
}
14471447

14481448
if (wNBytes & 0x01)
14491449
{
14501450
temp = *pdwVal;
1451-
pdwVal += PMA_STRIDE;
1451+
pdwVal += FSDEV_PMA_STRIDE;
14521452
*dstVal++ = ((temp >> 0) & 0xFF);
14531453
}
14541454
return true;
@@ -1475,7 +1475,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
14751475
// We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
14761476
// last lin byte will be combined with wrapped part
14771477
// To ensure PMA is always access aligned (src aligned to 16 or 32 bit)
1478-
#ifdef PMA_32BIT_ACCESS
1478+
#ifdef FSDEV_BUS_32BIT
14791479
if((cnt_lin & 0x03) && cnt_wrap)
14801480
{
14811481
// Copy first linear part

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