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# define DCD_STM32_BTABLE_BASE 0U
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#endif
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- #ifndef DCD_STM32_BTABLE_LENGTH
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- # define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE)
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+ #ifndef DCD_STM32_BTABLE_SIZE
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+ # define DCD_STM32_BTABLE_SIZE (FSDEV_PMA_SIZE - DCD_STM32_BTABLE_BASE)
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#endif
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/***************************************************
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* Checks, structs, defines, function definitions, etc.
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*/
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TU_VERIFY_STATIC ((MAX_EP_COUNT ) <= STFSDEV_EP_COUNT , "Only 8 endpoints supported on the hardware" );
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- TU_VERIFY_STATIC (((DCD_STM32_BTABLE_BASE ) + (DCD_STM32_BTABLE_LENGTH ))<=( PMA_LENGTH ), "BTABLE does not fit in PMA RAM" );
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+ TU_VERIFY_STATIC (((DCD_STM32_BTABLE_BASE ) + (DCD_STM32_BTABLE_SIZE )) <= ( FSDEV_PMA_SIZE ), "BTABLE does not fit in PMA RAM" );
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TU_VERIFY_STATIC (((DCD_STM32_BTABLE_BASE ) % 8 ) == 0 , "BTABLE base must be aligned to 8 bytes" );
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//--------------------------------------------------------------------+
@@ -559,7 +559,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
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// Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
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pcd_set_ep_rx_status (USB ,0u ,USB_EP_RX_NAK );
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pcd_set_ep_tx_status (USB ,0u ,USB_EP_TX_NAK );
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- #ifdef PMA_32BIT_ACCESS
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+ #ifdef FSDEV_BUS_32BIT
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dcd_event_setup_received (0 , (uint8_t * )(USB_PMAADDR + pcd_get_ep_rx_address (USB , EPindex )), true);
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#else
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// The setup_received function uses memcpy, so this must first copy the setup data into
@@ -673,13 +673,13 @@ void dcd_int_handler(uint8_t rhport) {
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/* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
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if (int_status & USB_ISTR_SOF ) {
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- USB -> ISTR &= ~USB_ISTR_SOF ;
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+ USB -> ISTR = ( fsdev_bus_t ) ~USB_ISTR_SOF ;
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dcd_event_sof (0 , USB -> FNR & USB_FNR_FN , true);
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}
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if (int_status & USB_ISTR_RESET ) {
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// USBRST is start of reset.
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- USB -> ISTR &= ~USB_ISTR_RESET ;
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+ USB -> ISTR = ( fsdev_bus_t ) ~USB_ISTR_RESET ;
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dcd_handle_bus_reset ();
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dcd_event_bus_reset (0 , TUSB_SPEED_FULL , true);
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return ; // Don't do the rest of the things here; perhaps they've been cleared?
@@ -697,7 +697,7 @@ void dcd_int_handler(uint8_t rhport) {
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USB -> CNTR &= ~USB_CNTR_LPMODE ;
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USB -> CNTR &= ~USB_CNTR_FSUSP ;
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- USB -> ISTR &= ~USB_ISTR_WKUP ;
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+ USB -> ISTR = ( fsdev_bus_t ) ~USB_ISTR_WKUP ;
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dcd_event_bus_signal (0 , DCD_EVENT_RESUME , true);
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}
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@@ -711,7 +711,7 @@ void dcd_int_handler(uint8_t rhport) {
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USB -> CNTR |= USB_CNTR_LPMODE ;
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/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
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- USB -> ISTR &= ~USB_ISTR_SUSP ;
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+ USB -> ISTR = ( fsdev_bus_t ) ~USB_ISTR_SUSP ;
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dcd_event_bus_signal (0 , DCD_EVENT_SUSPEND , true);
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}
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@@ -724,7 +724,7 @@ void dcd_int_handler(uint8_t rhport) {
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{
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remoteWakeCountdown -- ;
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}
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- USB -> ISTR &= ~USB_ISTR_ESOF ;
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+ USB -> ISTR = ( fsdev_bus_t ) ~USB_ISTR_ESOF ;
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}
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}
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@@ -786,7 +786,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
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}
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// Ensure allocated buffer is aligned
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- #ifdef PMA_32BIT_ACCESS
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+ #ifdef FSDEV_BUS_32BIT
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length = (length + 3 ) & ~0x03 ;
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#else
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length = (length + 1 ) & ~0x01 ;
@@ -798,7 +798,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
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ep_buf_ptr = (uint16_t )(ep_buf_ptr + length ); // increment buffer pointer
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// Verify no overflow
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- TU_ASSERT (ep_buf_ptr <= PMA_LENGTH , 0xFFFF );
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+ TU_ASSERT (ep_buf_ptr <= FSDEV_PMA_SIZE , 0xFFFF );
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epXferCtl -> pma_ptr = addr ;
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epXferCtl -> pma_alloc_size = length ;
@@ -1227,7 +1227,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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}
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}
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- #ifdef PMA_32BIT_ACCESS
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+ #ifdef FSDEV_BUS_32BIT
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static bool dcd_write_packet_memory (uint16_t dst , const void * __restrict src , uint16_t wNBytes )
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{
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const uint8_t * srcVal = src ;
@@ -1283,15 +1283,15 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
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__IO uint16_t * pdwVal ;
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srcVal = src ;
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- pdwVal = & pma [PMA_STRIDE * (dst >> 1 )];
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+ pdwVal = & pma [FSDEV_PMA_STRIDE * (dst >> 1 )];
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while (n -- )
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{
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temp1 = (uint16_t )* srcVal ;
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srcVal ++ ;
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temp2 = temp1 | ((uint16_t )(((uint16_t )(* srcVal )) << 8U )) ;
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* pdwVal = temp2 ;
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- pdwVal += PMA_STRIDE ;
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+ pdwVal += FSDEV_PMA_STRIDE ;
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srcVal ++ ;
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}
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@@ -1323,7 +1323,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
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// We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
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// last lin byte will be combined with wrapped part
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// To ensure PMA is always access aligned (dst aligned to 16 or 32 bit)
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- #ifdef PMA_32BIT_ACCESS
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+ #ifdef FSDEV_BUS_32BIT
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if ((cnt_lin & 0x03 ) && cnt_wrap )
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{
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// Copy first linear part
@@ -1386,7 +1386,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
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return true;
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}
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- #ifdef PMA_32BIT_ACCESS
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+ #ifdef FSDEV_BUS_32BIT
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static bool dcd_read_packet_memory (void * __restrict dst , uint16_t src , uint16_t wNBytes )
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{
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uint8_t * dstVal = dst ;
@@ -1434,21 +1434,21 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
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__IO const uint16_t * pdwVal ;
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uint32_t temp ;
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- pdwVal = & pma [PMA_STRIDE * (src >> 1 )];
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+ pdwVal = & pma [FSDEV_PMA_STRIDE * (src >> 1 )];
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uint8_t * dstVal = (uint8_t * )dst ;
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while (n -- )
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{
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temp = * pdwVal ;
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- pdwVal += PMA_STRIDE ;
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+ pdwVal += FSDEV_PMA_STRIDE ;
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* dstVal ++ = ((temp >> 0 ) & 0xFF );
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* dstVal ++ = ((temp >> 8 ) & 0xFF );
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}
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if (wNBytes & 0x01 )
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{
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temp = * pdwVal ;
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- pdwVal += PMA_STRIDE ;
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+ pdwVal += FSDEV_PMA_STRIDE ;
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* dstVal ++ = ((temp >> 0 ) & 0xFF );
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}
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return true;
@@ -1475,7 +1475,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
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// We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
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// last lin byte will be combined with wrapped part
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// To ensure PMA is always access aligned (src aligned to 16 or 32 bit)
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- #ifdef PMA_32BIT_ACCESS
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+ #ifdef FSDEV_BUS_32BIT
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if ((cnt_lin & 0x03 ) && cnt_wrap )
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{
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// Copy first linear part
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