[CIR][CIRGen][Builtin][Neon] Lower neon_vshl_n_v and neon_vshlq_n_v (#965)

As title, but important step in this PR is to allow CIR ShiftOp to take
vector of int type as input type. As result, I added a verifier to
ShiftOp with 2 constraints

1. Input type either all vector or int type. This is consistent with
LLVM::ShlOp, vector shift amount is expected.
2. In the spirit of C99 6.5.7.3, shift amount type must be the same as
result type, the if vector type is used. (This is enforced in LLVM
lowering for scalar int type).

Author: ghehg

clang/include/clang/CIR/Dialect/IR/CIROps.td

@@ -1181,15 +1181,20 @@ def ShiftOp : CIR_Op<"shift", [Pure]> {
   let summary = "Shift";
   let description = [{
     Shift `left` or `right`, according to the first operand. Second operand is
-    the shift target and the third the amount.
+    the shift target and the third the amount. Second and the thrid operand can
+    be either integer type or vector of integer type. However, they must be
+    either all vector of integer type, or all integer type. If they are vectors,
+    each vector element of the shift target is shifted by the corresponding
+    shift amount in the shift amount vector. 
 
     ```mlir
     %7 = cir.shift(left, %1 : !u64i, %4 : !s32i) -> !u64i
+    %8 = cir.shift(left, %2 : !cir.vector<!s32i x 2>, %3 : !cir.vector<!s32i x 2>) -> !cir.vector<!s32i x 2>
     ```
   }];
 
-  let results = (outs CIR_IntType:$result);
-  let arguments = (ins CIR_IntType:$value, CIR_IntType:$amount,
+  let results = (outs CIR_AnyIntOrVecOfInt:$result);
+  let arguments = (ins CIR_AnyIntOrVecOfInt:$value, CIR_AnyIntOrVecOfInt:$amount,
                        UnitAttr:$isShiftleft);
 
   let assemblyFormat = [{
@@ -1200,8 +1205,7 @@ def ShiftOp : CIR_Op<"shift", [Pure]> {
     `)` `->` type($result) attr-dict
   }];
 
-  // Already covered by the traits
-  let hasVerifier = 0;
+  let hasVerifier = 1;
 }
 
 //===----------------------------------------------------------------------===//

clang/include/clang/CIR/Dialect/IR/CIRTypes.td

@@ -537,6 +537,9 @@ def IntegerVector : Type<
     ]>, "!cir.vector of !cir.int"> {
 }
 
+// Constraints
+def CIR_AnyIntOrVecOfInt: AnyTypeOf<[CIR_IntType, IntegerVector]>;
+
 // Pointer to Arrays
 def ArrayPtr : Type<
     And<[

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

@@ -2205,10 +2205,10 @@ static int64_t getIntValueFromConstOp(mlir::Value val) {
 }
 
 /// This function `buildCommonNeonCallPattern0` implements a common way
-//  to generate neon intrinsic call that has following pattern:
-//  1. There is a need to cast result of the intrinsic call back to
-//     expression type.
-//  2. Function arg types are given, not deduced from actual arg types.
+///  to generate neon intrinsic call that has following pattern:
+///  1. There is a need to cast result of the intrinsic call back to
+///     expression type.
+///  2. Function arg types are given, not deduced from actual arg types.
 static mlir::Value
 buildCommonNeonCallPattern0(CIRGenFunction &cgf, std::string &intrincsName,
                             llvm::SmallVector<mlir::Type> argTypes,
@@ -2222,6 +2222,23 @@ buildCommonNeonCallPattern0(CIRGenFunction &cgf, std::string &intrincsName,
   return builder.createBitcast(res, resultType);
 }
 
+/// Build a constant shift amount vector of `vecTy` to shift a vector
+/// Here `shitfVal` is a constant integer that will be splated into a
+/// a const vector of `vecTy` which is the return of this function
+static mlir::Value buildNeonShiftVector(CIRGenBuilderTy &builder,
+                                        mlir::Value shiftVal,
+                                        mlir::cir::VectorType vecTy,
+                                        mlir::Location loc, bool neg) {
+  int shiftAmt = getIntValueFromConstOp(shiftVal);
+  llvm::SmallVector<mlir::Attribute> vecAttr{
+      vecTy.getSize(),
+      // ConstVectorAttr requires cir::IntAttr
+      mlir::cir::IntAttr::get(vecTy.getEltType(), shiftAmt)};
+  mlir::cir::ConstVectorAttr constVecAttr = mlir::cir::ConstVectorAttr::get(
+      vecTy, mlir::ArrayAttr::get(builder.getContext(), vecAttr));
+  return builder.create<mlir::cir::ConstantOp>(loc, vecTy, constVecAttr);
+}
+
 mlir::Value CIRGenFunction::buildCommonNeonBuiltinExpr(
     unsigned builtinID, unsigned llvmIntrinsic, unsigned altLLVMIntrinsic,
     const char *nameHint, unsigned modifier, const CallExpr *e,
@@ -2298,6 +2315,13 @@ mlir::Value CIRGenFunction::buildCommonNeonBuiltinExpr(
                              : "llvm.aarch64.neon.sqrdmulh.lane",
                          resTy, getLoc(e->getExprLoc()));
   }
+  case NEON::BI__builtin_neon_vshl_n_v:
+  case NEON::BI__builtin_neon_vshlq_n_v: {
+    mlir::Location loc = getLoc(e->getExprLoc());
+    ops[1] = buildNeonShiftVector(builder, ops[1], vTy, loc, false);
+    return builder.create<mlir::cir::ShiftOp>(
+        loc, vTy, builder.createBitcast(ops[0], vTy), ops[1], true);
+  }
   }
 
   // This second switch is for the intrinsics that might have a more generic

clang/lib/CIR/Dialect/IR/CIRDialect.cpp

@@ -3953,6 +3953,23 @@ LogicalResult BinOp::verify() {
   return mlir::success();
 }
 
+//===----------------------------------------------------------------------===//
+// ShiftOp Definitions
+//===----------------------------------------------------------------------===//
+LogicalResult ShiftOp::verify() {
+  mlir::Operation *op = getOperation();
+  mlir::Type resType = getResult().getType();
+  bool isOp0Vec = mlir::isa<mlir::cir::VectorType>(op->getOperand(0).getType());
+  bool isOp1Vec = mlir::isa<mlir::cir::VectorType>(op->getOperand(1).getType());
+  if (isOp0Vec != isOp1Vec)
+    return emitOpError() << "input types cannot be one vector and one scalar";
+  if (isOp1Vec && op->getOperand(1).getType() != resType) {
+    return emitOpError() << "shift amount must have the type of the result "
+                         << "if it is vector shift";
+  }
+  return mlir::success();
+}
+
 //===----------------------------------------------------------------------===//
 // LabelOp Definitions
 //===----------------------------------------------------------------------===//

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

@@ -2773,24 +2773,40 @@ class CIRShiftOpLowering
     auto cirAmtTy =
         mlir::dyn_cast<mlir::cir::IntType>(op.getAmount().getType());
     auto cirValTy = mlir::dyn_cast<mlir::cir::IntType>(op.getValue().getType());
+
+    // Operands could also be vector type
+    auto cirAmtVTy =
+        mlir::dyn_cast<mlir::cir::VectorType>(op.getAmount().getType());
+    auto cirValVTy =
+        mlir::dyn_cast<mlir::cir::VectorType>(op.getValue().getType());
     auto llvmTy = getTypeConverter()->convertType(op.getType());
     mlir::Value amt = adaptor.getAmount();
     mlir::Value val = adaptor.getValue();
 
-    assert(cirValTy && cirAmtTy && "non-integer shift is NYI");
-    assert(cirValTy == op.getType() && "inconsistent operands' types NYI");
+    assert(((cirValTy && cirAmtTy) || (cirAmtVTy && cirValVTy)) &&
+           "shift input type must be integer or vector type, otherwise NYI");
+
+    assert((cirValTy == op.getType() || cirValVTy == op.getType()) &&
+           "inconsistent operands' types NYI");
 
     // Ensure shift amount is the same type as the value. Some undefined
     // behavior might occur in the casts below as per [C99 6.5.7.3].
-    amt = getLLVMIntCast(rewriter, amt, mlir::cast<mlir::IntegerType>(llvmTy),
-                         !cirAmtTy.isSigned(), cirAmtTy.getWidth(),
-                         cirValTy.getWidth());
+    // Vector type shift amount needs no cast as type consistency is expected to
+    // be already be enforced at CIRGen.
+    if (cirAmtTy)
+      amt = getLLVMIntCast(rewriter, amt, mlir::cast<mlir::IntegerType>(llvmTy),
+                           !cirAmtTy.isSigned(), cirAmtTy.getWidth(),
+                           cirValTy.getWidth());
 
     // Lower to the proper LLVM shift operation.
     if (op.getIsShiftleft())
       rewriter.replaceOpWithNewOp<mlir::LLVM::ShlOp>(op, llvmTy, val, amt);
     else {
-      if (cirValTy.isUnsigned())
+      bool isUnSigned =
+          cirValTy ? !cirValTy.isSigned()
+                   : !mlir::cast<mlir::cir::IntType>(cirValVTy.getEltType())
+                          .isSigned();
+      if (isUnSigned)
         rewriter.replaceOpWithNewOp<mlir::LLVM::LShrOp>(op, llvmTy, val, amt);
       else
         rewriter.replaceOpWithNewOp<mlir::LLVM::AShrOp>(op, llvmTy, val, amt);