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[RISCV] Simplify macros used for commuting vector multiply-accumulate instructions. NFC (#144169)
Inline some macros that were only instantiated once. Remove unused macros. #undef macros when finished with them
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 22 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -3573,24 +3573,15 @@ std::string RISCVInstrInfo::createMIROperandComment(
35733573
#define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL) \
35743574
RISCV::PseudoV##OP##_##TYPE##_##LMUL
35753575

3576-
#define CASE_VMA_OPCODE_LMULS_M1(OP, TYPE) \
3577-
CASE_VMA_OPCODE_COMMON(OP, TYPE, M1): \
3576+
#define CASE_VMA_OPCODE_LMULS(OP, TYPE) \
3577+
CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8): \
3578+
case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4): \
3579+
case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2): \
3580+
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M1): \
35783581
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M2): \
35793582
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M4): \
35803583
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M8)
35813584

3582-
#define CASE_VMA_OPCODE_LMULS_MF2(OP, TYPE) \
3583-
CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2): \
3584-
case CASE_VMA_OPCODE_LMULS_M1(OP, TYPE)
3585-
3586-
#define CASE_VMA_OPCODE_LMULS_MF4(OP, TYPE) \
3587-
CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4): \
3588-
case CASE_VMA_OPCODE_LMULS_MF2(OP, TYPE)
3589-
3590-
#define CASE_VMA_OPCODE_LMULS(OP, TYPE) \
3591-
CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8): \
3592-
case CASE_VMA_OPCODE_LMULS_MF4(OP, TYPE)
3593-
35943585
// VFMA instructions are SEW specific.
35953586
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW) \
35963587
RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW
@@ -3790,29 +3781,15 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
37903781
Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
37913782
break;
37923783

3793-
#define CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE) \
3784+
#define CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \
3785+
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
3786+
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
3787+
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
37943788
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
37953789
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
37963790
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
37973791
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
37983792

3799-
#define CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE) \
3800-
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
3801-
CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)
3802-
3803-
#define CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE) \
3804-
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
3805-
CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)
3806-
3807-
#define CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \
3808-
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
3809-
CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
3810-
3811-
#define CASE_VMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \
3812-
CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16) \
3813-
CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32) \
3814-
CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64)
3815-
38163793
// VFMA depends on SEW.
38173794
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW) \
38183795
case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_##SEW: \
@@ -3829,18 +3806,14 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
38293806
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2, SEW) \
38303807
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)
38313808

3832-
#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP) \
3833-
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16) \
3834-
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \
3835-
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)
3836-
38373809
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW) \
38383810
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW) \
38393811
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)
38403812

3841-
#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE, SEW) \
3842-
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8, SEW) \
3843-
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)
3813+
#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP) \
3814+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16) \
3815+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \
3816+
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)
38443817

38453818
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \
38463819
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16, E16) \
@@ -3963,6 +3936,15 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
39633936
return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
39643937
}
39653938

3939+
#undef CASE_VMA_CHANGE_OPCODE_COMMON
3940+
#undef CASE_VMA_CHANGE_OPCODE_LMULS
3941+
#undef CASE_VFMA_CHANGE_OPCODE_COMMON
3942+
#undef CASE_VFMA_CHANGE_OPCODE_LMULS_M1
3943+
#undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF2
3944+
#undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF4
3945+
#undef CASE_VFMA_CHANGE_OPCODE_VV
3946+
#undef CASE_VFMA_CHANGE_OPCODE_SPLATS
3947+
39663948
#undef CASE_RVV_OPCODE_UNMASK_LMUL
39673949
#undef CASE_RVV_OPCODE_MASK_LMUL
39683950
#undef CASE_RVV_OPCODE_LMUL
@@ -3974,9 +3956,6 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
39743956
#undef CASE_RVV_OPCODE
39753957

39763958
#undef CASE_VMA_OPCODE_COMMON
3977-
#undef CASE_VMA_OPCODE_LMULS_M1
3978-
#undef CASE_VMA_OPCODE_LMULS_MF2
3979-
#undef CASE_VMA_OPCODE_LMULS_MF4
39803959
#undef CASE_VMA_OPCODE_LMULS
39813960
#undef CASE_VFMA_OPCODE_COMMON
39823961
#undef CASE_VFMA_OPCODE_LMULS_M1

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