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Revert D155711 "[SimplifyCFG] Hoist common instructions on Switch."
This reverts commit 96ea48f. The change may cause Verifier.cpp error "musttail call must precede a ret with an optional bitcast"
1 parent 7691666 commit 9f4c9b9

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7 files changed

+317
-927
lines changed

7 files changed

+317
-927
lines changed

‎llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Lines changed: 146 additions & 224 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ entry:
7070
i64 4, label %sw.bb4
7171
]
7272
sw.bb0:
73-
call void asm sideeffect "nop", ""()
73+
call void asm sideeffect "", ""()
7474
ret void
7575
sw.bb1:
7676
call void asm sideeffect "", ""()

‎llvm/test/Transforms/SimplifyCFG/HoistCode.ll

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,21 @@ F: ; preds = %0
1919

2020
define void @foo_switch(i64 %C, ptr %P) {
2121
; CHECK-LABEL: @foo_switch(
22-
; CHECK-NEXT: common.ret:
23-
; CHECK-NEXT: store i32 7, ptr [[P:%.*]], align 4
22+
; CHECK-NEXT: switch i64 [[C:%.*]], label [[BB0:%.*]] [
23+
; CHECK-NEXT: i64 1, label [[BB1:%.*]]
24+
; CHECK-NEXT: i64 2, label [[BB2:%.*]]
25+
; CHECK-NEXT: ]
26+
; CHECK: common.ret:
2427
; CHECK-NEXT: ret void
28+
; CHECK: bb0:
29+
; CHECK-NEXT: store i32 7, ptr [[P:%.*]], align 4
30+
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
31+
; CHECK: bb1:
32+
; CHECK-NEXT: store i32 7, ptr [[P]], align 4
33+
; CHECK-NEXT: br label [[COMMON_RET]]
34+
; CHECK: bb2:
35+
; CHECK-NEXT: store i32 7, ptr [[P]], align 4
36+
; CHECK-NEXT: br label [[COMMON_RET]]
2537
;
2638
switch i64 %C, label %bb0 [
2739
i64 1, label %bb1

‎llvm/test/Transforms/SimplifyCFG/hoist-common-code-with-unreachable.ll

Lines changed: 21 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,25 @@
44
define i1 @common_instr_with_unreachable(i64 %a, i64 %b, i64 %c) {
55
; CHECK-LABEL: @common_instr_with_unreachable(
66
; CHECK-NEXT: start:
7+
; CHECK-NEXT: switch i64 [[A:%.*]], label [[UNREACHABLE:%.*]] [
8+
; CHECK-NEXT: i64 0, label [[BB0:%.*]]
9+
; CHECK-NEXT: i64 1, label [[BB1:%.*]]
10+
; CHECK-NEXT: i64 2, label [[BB2:%.*]]
11+
; CHECK-NEXT: ]
12+
; CHECK: unreachable:
13+
; CHECK-NEXT: unreachable
14+
; CHECK: bb0:
715
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[B:%.*]], [[C:%.*]]
8-
; CHECK-NEXT: ret i1 [[TMP0]]
16+
; CHECK-NEXT: br label [[EXIT:%.*]]
17+
; CHECK: bb1:
18+
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[B]], [[C]]
19+
; CHECK-NEXT: br label [[EXIT]]
20+
; CHECK: bb2:
21+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[B]], [[C]]
22+
; CHECK-NEXT: br label [[EXIT]]
23+
; CHECK: exit:
24+
; CHECK-NEXT: [[RESULT:%.*]] = phi i1 [ [[TMP0]], [[BB0]] ], [ [[TMP1]], [[BB1]] ], [ [[TMP2]], [[BB2]] ]
25+
; CHECK-NEXT: ret i1 [[RESULT]]
926
;
1027
start:
1128
switch i64 %a, label %unreachable [
@@ -37,90 +54,43 @@ exit: ; preds = %bb2, %bb1, %bb0
3754
define i1 @common_instr_with_unreachable_2(i64 %a, i64 %b, i64 %c) {
3855
; CHECK-LABEL: @common_instr_with_unreachable_2(
3956
; CHECK-NEXT: start:
40-
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[B:%.*]], [[C:%.*]]
41-
; CHECK-NEXT: ret i1 [[TMP0]]
42-
;
43-
start:
44-
switch i64 %a, label %bb1 [
45-
i64 0, label %bb0
46-
i64 1, label %unreachable
47-
i64 2, label %bb2
48-
]
49-
50-
unreachable:
51-
unreachable
52-
53-
bb0: ; preds = %start
54-
%0 = icmp eq i64 %b, %c
55-
br label %exit
56-
57-
bb1: ; preds = %start
58-
%1 = icmp eq i64 %b, %c
59-
br label %exit
60-
61-
bb2: ; preds = %start
62-
%2 = icmp eq i64 %b, %c
63-
br label %exit
64-
65-
exit: ; preds = %bb2, %bb1, %bb0
66-
%result = phi i1 [ %0, %bb0 ], [ %1, %bb1 ], [ %2, %bb2 ]
67-
ret i1 %result
68-
}
69-
70-
declare void @no_return()
71-
declare void @foo()
72-
73-
define i1 @not_only_unreachable(i64 %a, i64 %b, i64 %c) {
74-
; CHECK-LABEL: @not_only_unreachable(
75-
; CHECK-NEXT: start:
76-
; CHECK-NEXT: switch i64 [[A:%.*]], label [[UNREACHABLE:%.*]] [
57+
; CHECK-NEXT: switch i64 [[A:%.*]], label [[BB1:%.*]] [
7758
; CHECK-NEXT: i64 0, label [[BB0:%.*]]
78-
; CHECK-NEXT: i64 1, label [[BB1:%.*]]
7959
; CHECK-NEXT: i64 2, label [[BB2:%.*]]
8060
; CHECK-NEXT: ]
81-
; CHECK: unreachable:
82-
; CHECK-NEXT: call void @no_return()
83-
; CHECK-NEXT: unreachable
8461
; CHECK: bb0:
8562
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[B:%.*]], [[C:%.*]]
86-
; CHECK-NEXT: call void @foo()
8763
; CHECK-NEXT: br label [[EXIT:%.*]]
8864
; CHECK: bb1:
8965
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[B]], [[C]]
90-
; CHECK-NEXT: call void @foo()
9166
; CHECK-NEXT: br label [[EXIT]]
9267
; CHECK: bb2:
9368
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[B]], [[C]]
94-
; CHECK-NEXT: call void @foo()
9569
; CHECK-NEXT: br label [[EXIT]]
9670
; CHECK: exit:
9771
; CHECK-NEXT: [[RESULT:%.*]] = phi i1 [ [[TMP0]], [[BB0]] ], [ [[TMP1]], [[BB1]] ], [ [[TMP2]], [[BB2]] ]
9872
; CHECK-NEXT: ret i1 [[RESULT]]
9973
;
10074
start:
101-
switch i64 %a, label %unreachable [
75+
switch i64 %a, label %bb1 [
10276
i64 0, label %bb0
103-
i64 1, label %bb1
77+
i64 1, label %unreachable
10478
i64 2, label %bb2
10579
]
10680

10781
unreachable:
108-
call void @no_return()
10982
unreachable
11083

11184
bb0: ; preds = %start
11285
%0 = icmp eq i64 %b, %c
113-
call void @foo()
11486
br label %exit
11587

11688
bb1: ; preds = %start
11789
%1 = icmp eq i64 %b, %c
118-
call void @foo()
11990
br label %exit
12091

12192
bb2: ; preds = %start
12293
%2 = icmp eq i64 %b, %c
123-
call void @foo()
12494
br label %exit
12595

12696
exit: ; preds = %bb2, %bb1, %bb0

‎llvm/test/Transforms/SimplifyCFG/hoist-common-code.ll

Lines changed: 33 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -26,11 +26,27 @@ F: ; preds = %0
2626

2727
define void @test_switch(i64 %i, ptr %Q) {
2828
; CHECK-LABEL: @test_switch(
29-
; CHECK-NEXT: common.ret:
29+
; CHECK-NEXT: switch i64 [[I:%.*]], label [[BB0:%.*]] [
30+
; CHECK-NEXT: i64 1, label [[BB1:%.*]]
31+
; CHECK-NEXT: i64 2, label [[BB2:%.*]]
32+
; CHECK-NEXT: ]
33+
; CHECK: common.ret:
34+
; CHECK-NEXT: ret void
35+
; CHECK: bb0:
3036
; CHECK-NEXT: store i32 1, ptr [[Q:%.*]], align 4
3137
; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[Q]], align 4
3238
; CHECK-NEXT: call void @bar(i32 [[A]])
33-
; CHECK-NEXT: ret void
39+
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
40+
; CHECK: bb1:
41+
; CHECK-NEXT: store i32 1, ptr [[Q]], align 4
42+
; CHECK-NEXT: [[B:%.*]] = load i32, ptr [[Q]], align 4
43+
; CHECK-NEXT: call void @bar(i32 [[B]])
44+
; CHECK-NEXT: br label [[COMMON_RET]]
45+
; CHECK: bb2:
46+
; CHECK-NEXT: store i32 1, ptr [[Q]], align 4
47+
; CHECK-NEXT: [[C:%.*]] = load i32, ptr [[Q]], align 4
48+
; CHECK-NEXT: call void @bar(i32 [[C]])
49+
; CHECK-NEXT: br label [[COMMON_RET]]
3450
;
3551
switch i64 %i, label %bb0 [
3652
i64 1, label %bb1
@@ -53,41 +69,25 @@ bb2: ; preds = %0
5369
ret void
5470
}
5571

56-
; We ensure that we examine all instructions during each iteration to confirm the presence of a terminating one.
57-
define void @test_switch_reach_terminator(i64 %i, ptr %p) {
58-
; CHECK-LABEL: @test_switch_reach_terminator(
59-
; CHECK-NEXT: switch i64 [[I:%.*]], label [[BB0:%.*]] [
60-
; CHECK-NEXT: i64 1, label [[BB1:%.*]]
61-
; CHECK-NEXT: i64 2, label [[COMMON_RET:%.*]]
62-
; CHECK-NEXT: ]
63-
; CHECK: common.ret:
64-
; CHECK-NEXT: ret void
65-
; CHECK: bb0:
66-
; CHECK-NEXT: store i32 1, ptr [[P:%.*]], align 4
67-
; CHECK-NEXT: br label [[COMMON_RET]]
68-
; CHECK: bb1:
69-
; CHECK-NEXT: store i32 2, ptr [[P]], align 4
70-
; CHECK-NEXT: br label [[COMMON_RET]]
71-
;
72-
switch i64 %i, label %bb0 [
73-
i64 1, label %bb1
74-
i64 2, label %bb2
75-
]
76-
bb0: ; preds = %0
77-
store i32 1, ptr %p
78-
ret void
79-
bb1: ; preds = %0
80-
store i32 2, ptr %p
81-
ret void
82-
bb2: ; preds = %0
83-
ret void
84-
}
85-
8672
define i1 @common_instr_on_switch(i64 %a, i64 %b, i64 %c) unnamed_addr {
8773
; CHECK-LABEL: @common_instr_on_switch(
8874
; CHECK-NEXT: start:
75+
; CHECK-NEXT: switch i64 [[A:%.*]], label [[BB0:%.*]] [
76+
; CHECK-NEXT: i64 1, label [[BB1:%.*]]
77+
; CHECK-NEXT: i64 2, label [[BB2:%.*]]
78+
; CHECK-NEXT: ]
79+
; CHECK: bb0:
8980
; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[B:%.*]], [[C:%.*]]
90-
; CHECK-NEXT: ret i1 [[TMP0]]
81+
; CHECK-NEXT: br label [[EXIT:%.*]]
82+
; CHECK: bb1:
83+
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[B]], [[C]]
84+
; CHECK-NEXT: br label [[EXIT]]
85+
; CHECK: bb2:
86+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[B]], [[C]]
87+
; CHECK-NEXT: br label [[EXIT]]
88+
; CHECK: exit:
89+
; CHECK-NEXT: [[RESULT:%.*]] = phi i1 [ [[TMP0]], [[BB0]] ], [ [[TMP1]], [[BB1]] ], [ [[TMP2]], [[BB2]] ]
90+
; CHECK-NEXT: ret i1 [[RESULT]]
9191
;
9292
start:
9393
switch i64 %a, label %bb0 [

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