implemented eltwise 'Equal' operation #30293
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build_jenkins |
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@madhurthareja thank you for the contribution! Please take a look at the left comments and fix them.
If you have some questions regarding build and launching tests, please feel free to ask them. But firstly please read the documentation - how to cross-compile OpenVINO for RISC-V and use emulator.
| // Use the RISC-V vector instruction for equality comparison | ||
| h->vmseq_vv(dst, src0, src1); // Set dst[i] = 1 if src0[i] == src1[i], else 0 |
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You're closer to the right implementation! But:
- The current JIT emitter should work with FP32 values (floating points values). We should use instructions which works with such values (not integer). Please take a look at section "13.13. Vector Floating-Point Compare Instructions" in the doc. Currently you use
vmseqinstruction which should be used for comparison of integer values. Please replace it with correct instruction. - Also since we work with FP32 values here, the destination vector should store values in FP32 format where
True = 1 = 0x3f800000andFalse = 0 = 0x0. Please take a look at he impl on ARM64 using SIMD. It might be useful for you. - Some hint: probably you need to use mask vector register (
mask_vreg())
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Launched GHA, many Equal tests are failed:
[ RUN ] smoke_CompareWithRefs/ComparisonLayerTest.Inference/IS=([]_[])_TS={(1)_(1)}_comparisonOpType=Equal_secondInputType=PARAMETER_in_type=f32_targetDevice=CPU
MEM_USAGE=4401632KB
Expected: 1 Actual: 0 Coordinate: 0 Diff: 1 calculated_abs_threshold: 0.000100119 abs_threshold: 1.19209e-07 rel_threshold: 0.0001
src/tests/functional/shared_test_classes/src/base/ov_subgraph.cpp:97: Failure
[ COMPARATION ] COMPARATION IS FAILED!
[ FAILED ] smoke_CompareWithRefs/ComparisonLayerTest.Inference/IS=([]_[])_TS={(1)_(1)}_comparisonOpType=Equal_secondInputType=PARAMETER_in_type=f32_targetDevice=CPU, where GetParam() = ({ ({}, { { 1 } }), ({}, { { 1 } }) }, Equal, PARAMETER, f32, "CPU", {}) (119 ms)
I believe that my previous comment will help you to fix it 😊
src/plugins/intel_cpu/src/emitters/plugin/riscv64/jit_eltwise_emitters.hpp
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src/plugins/intel_cpu/src/emitters/plugin/riscv64/jit_eltwise_emitters.hpp
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src/plugins/intel_cpu/src/nodes/kernels/riscv64/jit_uni_eltwise_generic.cpp
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src/plugins/intel_cpu/tests/functional/custom/single_layer_tests/classes/activation.cpp
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Hi! @a-sidorova I checked the documentation and tried implementing it, but I'm unable to find a way to emulate it on Arm64. I suppose it's not supported. Is it? If not, you could link me to the right page of documentation if I missed something. |
src/plugins/intel_cpu/src/nodes/kernels/riscv64/jit_uni_eltwise_generic.cpp
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src/plugins/intel_cpu/src/nodes/kernels/riscv64/jit_uni_eltwise_generic.cpp
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Could you tell me please if you tried to build xuantie-gnu-toolchain or riscv-gnu-toolchain with I don't see any restrictions related to CPUs in toolchains... I suppose it should work on arm64 even 🤔 So if you tried and faced with some problems, could you please share them? I will try to help with them 😊 |
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By the way, the documentation mentions only x64 platforms because we validated the cross-compilation workflow only on x64 CPUs. But if you try to cross-compile it and emulate tests on ARM64 platforms, we will be able to update our documentation thank your support :) |
Sure I'll try it. It might take a while, but I suppose I'll be able to emulate it. |
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