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Merge branch 'net-ethernet-ti-k3-introduce-common-platform-time-sync-driver-cpts'
Grygorii Strashko says: ==================== net: ethernet: ti: k3: introduce common platform time sync driver - cpts This series introduced support for significantly upgraded TI A65x/J721E Common platform time sync (CPTS) modules which are part of AM65xx Time Synchronization Architecture [1]. The TI A65x/J721E now contain more than one CPTS instance: - MCU CPSW CPTS (IEEE 1588 compliant) - Main NAVSS CPTS (central) - PCIe CPTS(s) (PTM compliant) - J721E: Main CPSW9g CPTS (IEEE 1588 compliant) which can work as separately as interact to each other through Time Sync Router (TSR) and Compare Event Router (CER). In addition there are also ICSS-G IEP blocks which can perform similar timsync functions, but require FW support. More info also available in TRM [2][3]. Not all above modules are available to the Linux by as of now as some of them are reserved for RTOS/FW purposes. The scope of this submission is TI A65x/J721E CPSW CPTS and Main NAVSS CPTS, and TSR was used for testing purposes. +---------------------------+ | MCU CPSW | +-------------------+ +------------------------+ | TS | | Main Navss CPTS | | Time Sync Router (TSR) | | +-------------+ | | | | | | | | | | HW1_TS +<----------+ | | +--------v-----+ +--+--+ | | | | | | CPTS | |Port | | ... | | | X+-->HW1_TS | | | | HW8_TS <------------<---------+ | X|-->HW2_TS | +--^--+ | | | | +--------------->HW3_TS | | | | | | | +--------------->HW4_TS | | | | | | | | | | | | | | | | | | | | | | | | Genf0 +-----------> (A)---------+ +<--------------+Genf0 | | | | | | | | | | | | | | ... | | +-----------> <---------------+Genf1 ESTf+-------+ | | | | | | | | | | | | | | +--------------+ | | Genf8 +---------->+ | | | | | | SYNC0 ... SYNC3 | | | +-------------------+ +------+------------+----+ +---------------------------+ + + X X (A) shows possible routing path for MCU CPSW CPTS Genf0 signal as an example. Main features of the new TI A65x/J721E CPTS modules are: - 64-bit timestamp/counter mode support in ns by using add_val - implemented in HW PPM and nudge adjustment. - control of time sync events via interrupt or polling - selection of multiple external reference clock sources - hardware timestamp of ext. inputs events (HWx_TS_PUSH) - periodic generator function outputs (TS_GENFx) - (CPSW only) Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn), which drives TSN schedule - timestamping of all RX packets bypassing CPTS FIFO Patch 1 - DT bindings Patch 2 - the AM65x/J721E driver Patch 3 - enables packet timestamping support in TI AM65x/J721E MCU CPSW driver. Patches 4-7 - DT updates. === PTP Testing: phc2sys -s CLOCK_REALTIME -c eth0 -m -O 0 -u30 phc2sys[627.331]: eth0 rms 409912446712787392 max 1587584079521858304 freq -6665 +/- 35040 delay 832 +/- 27 phc2sys[657.335]: eth0 rms 33 max 66 freq -0 +/- 28 delay 820 +/- 30 phc2sys[687.339]: eth0 rms 37 max 70 freq -1 +/- 32 delay 830 +/- 29 phc2sys[717.343]: eth0 rms 33 max 71 freq -0 +/- 29 delay 828 +/- 23 phc2sys[747.346]: eth0 rms 35 max 75 freq -0 +/- 31 delay 829 +/- 26 phc2sys[777.350]: eth0 rms 37 max 68 freq -1 +/- 32 delay 825 +/- 25 phc2sys[807.354]: eth0 rms 28 max 57 freq -1 +/- 25 delay 824 +/- 21 phc2sys[837.358]: eth0 rms 43 max 81 freq -1 +/- 37 delay 836 +/- 23 phc2sys[867.361]: eth0 rms 33 max 74 freq +0 +/- 29 delay 828 +/- 24 phc2sys[897.365]: eth0 rms 35 max 77 freq -2 +/- 30 delay 824 +/- 25 phc2sys[927.369]: eth0 rms 28 max 50 freq +0 +/- 25 delay 825 +/- 25 ptp4l -P -2 -H -i eth0 -l 6 -m -q -p /dev/ptp1 -f ptp.cfg -s ptp4l[22095.754]: port 1: MASTER to UNCALIBRATED on RS_SLAVE ptp4l[22097.754]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[22159.757]: rms 317 max 1418 freq +79 +/- 186 delay 410 +/- 1 ptp4l[22223.760]: rms 9 max 24 freq +42 +/- 12 delay 409 +/- 1 ptp4l[22287.763]: rms 10 max 28 freq +41 +/- 11 delay 410 +/- 1 ptp4l[22351.767]: rms 10 max 26 freq +34 +/- 12 delay 410 +/- 1 ptp4l[22415.770]: rms 10 max 26 freq +49 +/- 14 delay 410 +/- 1 === Ext. HW_TS and Genf testing: For testing purposes Time Sync Router (TSR) can be modeled in DT as pin controller + timesync_router: timesync_router@A40000 { + compatible = "pinctrl-single"; + reg = <0x0 0xA40000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x800007ff>; + }; then signals routing can be done in board file, for example: +#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x80000000 | val) + +&timesync_router { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpts>; + + /* Example of the timesync routing */ + mcu_cpts: mcu_cpts { + pinctrl-single,pins = < + /* [cpts genf1] in13 -> out25 [cpts hw4_push] */ + TS_OFFSET(25, 13) + /* [cpts genf1] in13 -> out0 [main cpts hw1_push] */ + TS_OFFSET(0, 13) + /* [main cpts genf0] in4 -> out1 [main cpts hw2_push] */ + TS_OFFSET(1, 4) + /* [main cpts genf0] in4 -> out24 [cpts hw3_push] */ + TS_OFFSET(24, 4) + >; + }; +}; will create link: cpsw cpts Genf1 -> main cpts hw1_push -> cpsw cpts hw4_push main cpts Genf0 -> main cpts hw2_push -> cpsw cpts hw3_push testptp -d /dev/ptp0 -i 0 -p 1000000000 periodic output request okay testptp -d /dev/ptp0 -i 1 -e 5 external time stamp request okay event index 1 at 22583.000000025 event index 1 at 22584.000000025 event index 1 at 22585.000000025 event index 1 at 22586.000000025 event index 1 at 22587.000000025 testptp -d /dev/ptp1 -i 2 -e 5 external time stamp request okay event index 2 at 1587606764.249304554 event index 2 at 1587606765.249304467 event index 2 at 1587606766.249304380 event index 2 at 1587606767.249304293 event index 2 at 1587606768.249304206 [1] https://www.ti.com/lit/pdf/spracp7 [2] https://www.ti.com/lit/pdf/sprz452 [3] https://www.ti.com/lit/pdf/spruil1 ==================== Signed-off-by: David S. Miller <[email protected]>
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‎Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

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@@ -144,6 +144,13 @@ patternProperties:
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description:
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CPSW MDIO bus.
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"^cpts$":
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type: object
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allOf:
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- $ref: "ti,am654-cpts.yaml#"
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description:
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CPSW Common Platform Time Sync (CPTS) module.
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/ti,am654-cpts.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module Device Tree Bindings
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maintainers:
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- Grygorii Strashko <[email protected]>
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- Sekhar Nori <[email protected]>
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description: |+
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The TI AM654x/J721E CPTS module is used to facilitate host control of time
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sync operations.
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Main features of CPTS module are
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- selection of multiple external clock sources
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- Software control of time sync events via interrupt or polling
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- 64-bit timestamp mode in ns with PPM and nudge adjustment.
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- hardware timestamp push inputs (HWx_TS_PUSH)
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- timestamp counter compare output (TS_COMP)
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- timestamp counter bit output (TS_SYNC)
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- periodic Generator function outputs (TS_GENFx)
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- Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn) (TSN)
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- external hardware timestamp push inputs (HWx_TS_PUSH) timestamping
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Depending on integration it enables compliance with the IEEE 1588-2008
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standard for a precision clock synchronization protocol, Ethernet Enhanced
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Scheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time
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Measurement (PTM).
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TI AM654x/J721E SoCs has several similar CPTS modules integrated into the
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different parts of the system which could be synchronized with each other
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- Main CPTS
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- MCU CPSW CPTS with IEEE 1588-2008 support
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- PCIe subsystem CPTS for PTM support
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Depending on CPTS module integration and when CPTS is integral part of
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another module (MCU CPSW for example) "compatible" and "reg" can
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be omitted - parent module is fully responsible for CPTS enabling and
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configuration.
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properties:
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$nodename:
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pattern: "^cpts(@.*|-[0-9a-f])*$"
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compatible:
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oneOf:
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- const: ti,am65-cpts
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- const: ti,j721e-cpts
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reg:
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maxItems: 1
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description:
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The physical base address and size of CPTS IO range
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reg-names:
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items:
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- const: cpts
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clocks:
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description: CPTS reference clock
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clock-names:
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items:
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- const: cpts
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interrupts-extended:
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items:
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- description: CPTS events interrupt
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interrupt-names:
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items:
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- const: "cpts"
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ti,cpts-ext-ts-inputs:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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maximum: 8
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description:
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Number of hardware timestamp push inputs (HWx_TS_PUSH)
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ti,cpts-periodic-outputs:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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maximum: 8
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description:
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Number of timestamp Generator function outputs (TS_GENFx)
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refclk-mux:
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type: object
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description: CPTS reference clock multiplexer clock
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properties:
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'#clock-cells':
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const: 0
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clocks:
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maxItems: 8
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assigned-clocks:
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maxItems: 1
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assigned-clocks-parents:
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maxItems: 1
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required:
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- clocks
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required:
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- clocks
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- clock-names
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- interrupts-extended
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cpts@310d0000 {
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compatible = "ti,am65-cpts";
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reg = <0x0 0x310d0000 0x0 0x400>;
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reg-names = "cpts";
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clocks = <&main_cpts_mux>;
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clock-names = "cpts";
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interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-periodic-outputs = <6>;
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ti,cpts-ext-ts-inputs = <8>;
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main_cpts_mux: refclk-mux {
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#clock-cells = <0>;
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clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
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<&k3_clks 157 91>, <&k3_clks 157 77>,
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<&k3_clks 157 102>, <&k3_clks 157 80>,
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<&k3_clks 120 3>, <&k3_clks 121 3>;
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assigned-clocks = <&main_cpts_mux>;
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assigned-clock-parents = <&k3_clks 118 11>;
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};
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};
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- |
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cpts {
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clocks = <&k3_clks 18 2>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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};

‎arch/arm64/boot/dts/ti/k3-am65-main.dtsi

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@@ -570,6 +570,28 @@
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<0x5>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
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};
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cpts@310d0000 {
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compatible = "ti,am65-cpts";
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reg = <0x0 0x310d0000 0x0 0x400>;
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reg-names = "cpts";
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clocks = <&main_cpts_mux>;
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clock-names = "cpts";
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interrupts-extended = <&intr_main_navss 163 0>;
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interrupt-names = "cpts";
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ti,cpts-periodic-outputs = <6>;
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ti,cpts-ext-ts-inputs = <8>;
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main_cpts_mux: refclk-mux {
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#clock-cells = <0>;
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clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
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<&k3_clks 118 6>, <&k3_clks 118 3>,
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<&k3_clks 118 8>, <&k3_clks 118 14>,
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<&k3_clks 120 3>, <&k3_clks 121 3>;
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assigned-clocks = <&main_cpts_mux>;
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assigned-clock-parents = <&k3_clks 118 5>;
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};
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};
573595
};
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575597
main_gpio0: main_gpio0@600000 {

‎arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

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clock-names = "fck";
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bus_freq = <1000000>;
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};
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cpts {
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clocks = <&mcu_cpsw_cpts_mux>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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mcu_cpsw_cpts_mux: refclk-mux {
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#clock-cells = <0>;
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clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
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<&k3_clks 118 6>, <&k3_clks 118 3>,
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<&k3_clks 118 8>, <&k3_clks 118 14>,
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<&k3_clks 120 3>, <&k3_clks 121 3>;
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assigned-clocks = <&mcu_cpsw_cpts_mux>;
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assigned-clock-parents = <&k3_clks 118 5>;
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};
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};
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};
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};

‎arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

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<0x0c>; /* RX_UHCHAN */
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ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
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};
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cpts@310d0000 {
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compatible = "ti,j721e-cpts";
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reg = <0x0 0x310d0000 0x0 0x400>;
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reg-names = "cpts";
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clocks = <&k3_clks 201 1>;
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clock-names = "cpts";
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interrupts-extended = <&main_navss_intr 201 0>;
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interrupt-names = "cpts";
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ti,cpts-periodic-outputs = <6>;
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ti,cpts-ext-ts-inputs = <8>;
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};
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};
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259271
main_pmx0: pinmux@11c000 {

‎arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi

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clock-names = "fck";
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bus_freq = <1000000>;
340340
};
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cpts {
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clocks = <&k3_clks 18 2>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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};
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};
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};

‎drivers/net/ethernet/ti/Kconfig

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@@ -100,6 +100,7 @@ config TI_K3_AM65_CPSW_NUSS
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depends on ARCH_K3 && OF && TI_K3_UDMA_GLUE_LAYER
101101
select TI_DAVINCI_MDIO
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imply PHY_TI_GMII_SEL
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imply TI_AM65_CPTS
103104
help
104105
This driver supports TI K3 AM654/J721E CPSW2G Ethernet SubSystem.
105106
The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides
@@ -110,6 +111,20 @@ config TI_K3_AM65_CPSW_NUSS
110111
To compile this driver as a module, choose M here: the module
111112
will be called ti-am65-cpsw-nuss.
112113

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config TI_K3_AM65_CPTS
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tristate "TI K3 AM65x CPTS"
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depends on ARCH_K3 && OF && PTP_1588_CLOCK
117+
depends on PTP_1588_CLOCK
118+
select NET_PTP_CLASSIFY
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help
120+
Say y here to support the TI K3 AM65x CPTS with 1588 features such as
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PTP hardware clock for each CPTS device and network packets
122+
timestamping where applicable.
123+
Depending on integration CPTS blocks enable compliance with
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the IEEE 1588-2008 standard for a precision clock synchronization
125+
protocol, Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn)
126+
and PCIe Subsystem Precision Time Measurement (PTM).
127+
113128
config TI_KEYSTONE_NETCP
114129
tristate "TI Keystone NETCP Core Support"
115130
select TI_DAVINCI_MDIO

‎drivers/net/ethernet/ti/Makefile

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@@ -26,3 +26,4 @@ keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o cpsw_ale.
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2727
obj-$(CONFIG_TI_K3_AM65_CPSW_NUSS) += ti-am65-cpsw-nuss.o
2828
ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o k3-cppi-desc-pool.o
29+
obj-$(CONFIG_TI_K3_AM65_CPTS) += am65-cpts.o

‎drivers/net/ethernet/ti/am65-cpsw-ethtool.c

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#include "am65-cpsw-nuss.h"
1414
#include "cpsw_ale.h"
15+
#include "am65-cpts.h"
1516

1617
#define AM65_CPSW_REGDUMP_VER 0x1
1718

@@ -694,6 +695,27 @@ static void am65_cpsw_get_ethtool_stats(struct net_device *ndev,
694695
hw_stats[i].offset);
695696
}
696697

698+
static int am65_cpsw_get_ethtool_ts_info(struct net_device *ndev,
699+
struct ethtool_ts_info *info)
700+
{
701+
struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
702+
703+
if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
704+
return ethtool_op_get_ts_info(ndev, info);
705+
706+
info->so_timestamping =
707+
SOF_TIMESTAMPING_TX_HARDWARE |
708+
SOF_TIMESTAMPING_TX_SOFTWARE |
709+
SOF_TIMESTAMPING_RX_HARDWARE |
710+
SOF_TIMESTAMPING_RX_SOFTWARE |
711+
SOF_TIMESTAMPING_SOFTWARE |
712+
SOF_TIMESTAMPING_RAW_HARDWARE;
713+
info->phc_index = am65_cpts_phc_index(common->cpts);
714+
info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
715+
info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
716+
return 0;
717+
}
718+
697719
static u32 am65_cpsw_get_ethtool_priv_flags(struct net_device *ndev)
698720
{
699721
struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
@@ -730,7 +752,7 @@ const struct ethtool_ops am65_cpsw_ethtool_ops_slave = {
730752
.get_sset_count = am65_cpsw_get_sset_count,
731753
.get_strings = am65_cpsw_get_strings,
732754
.get_ethtool_stats = am65_cpsw_get_ethtool_stats,
733-
.get_ts_info = ethtool_op_get_ts_info,
755+
.get_ts_info = am65_cpsw_get_ethtool_ts_info,
734756
.get_priv_flags = am65_cpsw_get_ethtool_priv_flags,
735757
.set_priv_flags = am65_cpsw_set_ethtool_priv_flags,
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