|
| 1 | +// SPDX-License-Identifier: Apache-2.0 OR MIT |
| 2 | +// |
| 3 | +// Copyright (c) 2020-2022 by the author(s) |
| 4 | +// |
| 5 | +// Author(s): |
| 6 | +// - Chris Brown <[email protected]> |
| 7 | + |
| 8 | +//! Debug Data Transfer Register, half-duplex |
| 9 | +//! |
| 10 | +//! Transfers 64 bits of data between the PE and an external debugger. Can transfer both ways using |
| 11 | +//! only a single register. |
| 12 | +
|
| 13 | +use tock_registers::{ |
| 14 | + interfaces::{Readable, Writeable}, |
| 15 | + register_bitfields, |
| 16 | +}; |
| 17 | + |
| 18 | +register_bitfields! {u64, |
| 19 | + pub DBGDTR_EL0 [ |
| 20 | + /// Writes to this register set DTRRX to the value in this field and do not change RXfull. |
| 21 | + /// |
| 22 | + /// Reads of this register: |
| 23 | + /// |
| 24 | + /// - If RXfull is set to 1, return the last value written to DTRTX. |
| 25 | + /// - If RXfull is set to 0, return an UNKNOWN value. |
| 26 | + /// |
| 27 | + /// After the read, RXfull is cleared to 0. |
| 28 | + HighWord OFFSET(32) NUMBITS(32) [], |
| 29 | + |
| 30 | + /// Writes to this register set DTRTX to the value in this field and set TXfull to 1. |
| 31 | + /// |
| 32 | + /// Reads of this register: |
| 33 | + /// |
| 34 | + /// - If RXfull is set to 1, return the last value written to DTRRX. |
| 35 | + /// - If RXfull is set to 0, return an UNKNOWN value. |
| 36 | + /// |
| 37 | + /// After the read, RXfull is cleared to 0. |
| 38 | + LowWord OFFSET(0) NUMBITS(32) [] |
| 39 | + ] |
| 40 | +} |
| 41 | + |
| 42 | +pub struct Reg; |
| 43 | + |
| 44 | +impl Readable for Reg { |
| 45 | + type T = u64; |
| 46 | + type R = DBGDTR_EL0::Register; |
| 47 | + |
| 48 | + sys_coproc_read_raw!(u64, "DBGDTR_EL0", "x"); |
| 49 | +} |
| 50 | + |
| 51 | +impl Writeable for Reg { |
| 52 | + type T = u64; |
| 53 | + type R = DBGDTR_EL0::Register; |
| 54 | + |
| 55 | + sys_coproc_write_raw!(u64, "DBGDTR_EL0", "x"); |
| 56 | +} |
| 57 | + |
| 58 | +pub const DBGDTR_EL0: Reg = Reg {}; |
0 commit comments