We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent e38a68d commit 9418b6cCopy full SHA for 9418b6c
src/register/mip.rs
@@ -80,18 +80,12 @@ set_clear_csr!(
80
set_clear_csr!(
81
/// Supervisor Software Interrupt Pending
82
, set_ssoft, clear_ssoft, 1 << 1);
83
-set_clear_csr!(
84
- /// Machine Software Interrupt Pending
85
- , set_msoft, clear_msoft, 1 << 3);
86
87
/// User Timer Interrupt Pending
88
, set_utimer, clear_utimer, 1 << 4);
89
90
/// Supervisor Timer Interrupt Pending
91
, set_stimer, clear_stimer, 1 << 5);
92
93
- /// Machine Timer Interrupt Pending
94
- , set_mtimer, clear_mtimer, 1 << 7);
95
96
/// User External Interrupt Pending
97
, set_uext, clear_uext, 1 << 8);
0 commit comments