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shader_recompiler: Add swizzle support for unsupported formats. (#1869)
* shader_recompiler: Add swizzle support for unsupported formats. * renderer_vulkan: Rework MRT swizzles and add unsupported format swizzle support. * shader_recompiler: Clean up swizzle handling and handle ImageRead storage swizzle. * shader_recompiler: Fix type errors * liverpool_to_vk: Remove redundant clear color swizzles. * shader_recompiler: Reduce CompositeConstruct to constants where possible. * shader_recompiler: Fix ImageRead/Write and StoreBufferFormatF32 types. * amdgpu: Add a few more unsupported format remaps.
1 parent 284f473 commit 41d64a2

22 files changed

+522
-282
lines changed

‎CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -701,6 +701,7 @@ set(SHADER_RECOMPILER src/shader_recompiler/exception.h
701701
src/shader_recompiler/ir/post_order.h
702702
src/shader_recompiler/ir/program.cpp
703703
src/shader_recompiler/ir/program.h
704+
src/shader_recompiler/ir/reinterpret.h
704705
src/shader_recompiler/ir/reg.h
705706
src/shader_recompiler/ir/type.cpp
706707
src/shader_recompiler/ir/type.h

‎src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp

Lines changed: 80 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -6,16 +6,22 @@
66

77
namespace Shader::Backend::SPIRV {
88

9-
Id EmitCompositeConstructU32x2(EmitContext& ctx, Id e1, Id e2) {
10-
return ctx.OpCompositeConstruct(ctx.U32[2], e1, e2);
9+
template <typename... Args>
10+
Id EmitCompositeConstruct(EmitContext& ctx, IR::Inst* inst, Args&&... args) {
11+
return inst->AreAllArgsImmediates() ? ctx.ConstantComposite(args...)
12+
: ctx.OpCompositeConstruct(args...);
1113
}
1214

13-
Id EmitCompositeConstructU32x3(EmitContext& ctx, Id e1, Id e2, Id e3) {
14-
return ctx.OpCompositeConstruct(ctx.U32[3], e1, e2, e3);
15+
Id EmitCompositeConstructU32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) {
16+
return EmitCompositeConstruct(ctx, inst, ctx.U32[2], e1, e2);
1517
}
1618

17-
Id EmitCompositeConstructU32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4) {
18-
return ctx.OpCompositeConstruct(ctx.U32[4], e1, e2, e3, e4);
19+
Id EmitCompositeConstructU32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3) {
20+
return EmitCompositeConstruct(ctx, inst, ctx.U32[3], e1, e2, e3);
21+
}
22+
23+
Id EmitCompositeConstructU32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4) {
24+
return EmitCompositeConstruct(ctx, inst, ctx.U32[4], e1, e2, e3, e4);
1925
}
2026

2127
Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index) {
@@ -42,16 +48,30 @@ Id EmitCompositeInsertU32x4(EmitContext& ctx, Id composite, Id object, u32 index
4248
return ctx.OpCompositeInsert(ctx.U32[4], object, composite, index);
4349
}
4450

45-
Id EmitCompositeConstructF16x2(EmitContext& ctx, Id e1, Id e2) {
46-
return ctx.OpCompositeConstruct(ctx.F16[2], e1, e2);
51+
Id EmitCompositeShuffleU32x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
52+
return ctx.OpVectorShuffle(ctx.U32[2], composite1, composite2, comp0, comp1);
53+
}
54+
55+
Id EmitCompositeShuffleU32x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
56+
u32 comp2) {
57+
return ctx.OpVectorShuffle(ctx.U32[3], composite1, composite2, comp0, comp1, comp2);
4758
}
4859

49-
Id EmitCompositeConstructF16x3(EmitContext& ctx, Id e1, Id e2, Id e3) {
50-
return ctx.OpCompositeConstruct(ctx.F16[3], e1, e2, e3);
60+
Id EmitCompositeShuffleU32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
61+
u32 comp2, u32 comp3) {
62+
return ctx.OpVectorShuffle(ctx.U32[4], composite1, composite2, comp0, comp1, comp2, comp3);
5163
}
5264

53-
Id EmitCompositeConstructF16x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4) {
54-
return ctx.OpCompositeConstruct(ctx.F16[4], e1, e2, e3, e4);
65+
Id EmitCompositeConstructF16x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) {
66+
return EmitCompositeConstruct(ctx, inst, ctx.F16[2], e1, e2);
67+
}
68+
69+
Id EmitCompositeConstructF16x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3) {
70+
return EmitCompositeConstruct(ctx, inst, ctx.F16[3], e1, e2, e3);
71+
}
72+
73+
Id EmitCompositeConstructF16x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4) {
74+
return EmitCompositeConstruct(ctx, inst, ctx.F16[4], e1, e2, e3, e4);
5575
}
5676

5777
Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index) {
@@ -78,16 +98,30 @@ Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index
7898
return ctx.OpCompositeInsert(ctx.F16[4], object, composite, index);
7999
}
80100

81-
Id EmitCompositeConstructF32x2(EmitContext& ctx, Id e1, Id e2) {
82-
return ctx.OpCompositeConstruct(ctx.F32[2], e1, e2);
101+
Id EmitCompositeShuffleF16x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
102+
return ctx.OpVectorShuffle(ctx.F16[2], composite1, composite2, comp0, comp1);
103+
}
104+
105+
Id EmitCompositeShuffleF16x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
106+
u32 comp2) {
107+
return ctx.OpVectorShuffle(ctx.F16[3], composite1, composite2, comp0, comp1, comp2);
108+
}
109+
110+
Id EmitCompositeShuffleF16x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
111+
u32 comp2, u32 comp3) {
112+
return ctx.OpVectorShuffle(ctx.F16[4], composite1, composite2, comp0, comp1, comp2, comp3);
113+
}
114+
115+
Id EmitCompositeConstructF32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) {
116+
return EmitCompositeConstruct(ctx, inst, ctx.F32[2], e1, e2);
83117
}
84118

85-
Id EmitCompositeConstructF32x3(EmitContext& ctx, Id e1, Id e2, Id e3) {
86-
return ctx.OpCompositeConstruct(ctx.F32[3], e1, e2, e3);
119+
Id EmitCompositeConstructF32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3) {
120+
return EmitCompositeConstruct(ctx, inst, ctx.F32[3], e1, e2, e3);
87121
}
88122

89-
Id EmitCompositeConstructF32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4) {
90-
return ctx.OpCompositeConstruct(ctx.F32[4], e1, e2, e3, e4);
123+
Id EmitCompositeConstructF32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4) {
124+
return EmitCompositeConstruct(ctx, inst, ctx.F32[4], e1, e2, e3, e4);
91125
}
92126

93127
Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index) {
@@ -114,6 +148,20 @@ Id EmitCompositeInsertF32x4(EmitContext& ctx, Id composite, Id object, u32 index
114148
return ctx.OpCompositeInsert(ctx.F32[4], object, composite, index);
115149
}
116150

151+
Id EmitCompositeShuffleF32x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
152+
return ctx.OpVectorShuffle(ctx.F32[2], composite1, composite2, comp0, comp1);
153+
}
154+
155+
Id EmitCompositeShuffleF32x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
156+
u32 comp2) {
157+
return ctx.OpVectorShuffle(ctx.F32[3], composite1, composite2, comp0, comp1, comp2);
158+
}
159+
160+
Id EmitCompositeShuffleF32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
161+
u32 comp2, u32 comp3) {
162+
return ctx.OpVectorShuffle(ctx.F32[4], composite1, composite2, comp0, comp1, comp2, comp3);
163+
}
164+
117165
void EmitCompositeConstructF64x2(EmitContext&) {
118166
UNREACHABLE_MSG("SPIR-V Instruction");
119167
}
@@ -150,4 +198,18 @@ Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index
150198
return ctx.OpCompositeInsert(ctx.F64[4], object, composite, index);
151199
}
152200

201+
Id EmitCompositeShuffleF64x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
202+
return ctx.OpVectorShuffle(ctx.F64[2], composite1, composite2, comp0, comp1);
203+
}
204+
205+
Id EmitCompositeShuffleF64x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
206+
u32 comp2) {
207+
return ctx.OpVectorShuffle(ctx.F64[3], composite1, composite2, comp0, comp1, comp2);
208+
}
209+
210+
Id EmitCompositeShuffleF64x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
211+
u32 comp2, u32 comp3) {
212+
return ctx.OpVectorShuffle(ctx.F64[4], composite1, composite2, comp0, comp1, comp2, comp3);
213+
}
214+
153215
} // namespace Shader::Backend::SPIRV

‎src/shader_recompiler/backend/spirv/emit_spirv_image.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,7 @@ Id EmitImageRead(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod
238238
}
239239
texel = ctx.OpImageRead(color_type, image, coords, operands.mask, operands.operands);
240240
}
241-
return !texture.is_integer ? ctx.OpBitcast(ctx.U32[4], texel) : texel;
241+
return texture.is_integer ? ctx.OpBitcast(ctx.F32[4], texel) : texel;
242242
}
243243

244244
void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod, Id ms,
@@ -253,8 +253,8 @@ void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id
253253
} else if (Sirit::ValidId(lod)) {
254254
LOG_WARNING(Render, "Image write with LOD not supported by driver");
255255
}
256-
ctx.OpImageWrite(image, coords, ctx.OpBitcast(color_type, color), operands.mask,
257-
operands.operands);
256+
const Id texel = texture.is_integer ? ctx.OpBitcast(color_type, color) : color;
257+
ctx.OpImageWrite(image, coords, texel, operands.mask, operands.operands);
258258
}
259259

260260
} // namespace Shader::Backend::SPIRV

‎src/shader_recompiler/backend/spirv/emit_spirv_instructions.h

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -120,33 +120,48 @@ Id EmitSharedAtomicSMin32(EmitContext& ctx, Id offset, Id value);
120120
Id EmitSharedAtomicAnd32(EmitContext& ctx, Id offset, Id value);
121121
Id EmitSharedAtomicOr32(EmitContext& ctx, Id offset, Id value);
122122
Id EmitSharedAtomicXor32(EmitContext& ctx, Id offset, Id value);
123-
Id EmitCompositeConstructU32x2(EmitContext& ctx, Id e1, Id e2);
124-
Id EmitCompositeConstructU32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
125-
Id EmitCompositeConstructU32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
123+
Id EmitCompositeConstructU32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2);
124+
Id EmitCompositeConstructU32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3);
125+
Id EmitCompositeConstructU32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4);
126126
Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index);
127127
Id EmitCompositeExtractU32x3(EmitContext& ctx, Id composite, u32 index);
128128
Id EmitCompositeExtractU32x4(EmitContext& ctx, Id composite, u32 index);
129129
Id EmitCompositeInsertU32x2(EmitContext& ctx, Id composite, Id object, u32 index);
130130
Id EmitCompositeInsertU32x3(EmitContext& ctx, Id composite, Id object, u32 index);
131131
Id EmitCompositeInsertU32x4(EmitContext& ctx, Id composite, Id object, u32 index);
132-
Id EmitCompositeConstructF16x2(EmitContext& ctx, Id e1, Id e2);
133-
Id EmitCompositeConstructF16x3(EmitContext& ctx, Id e1, Id e2, Id e3);
134-
Id EmitCompositeConstructF16x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
132+
Id EmitCompositeShuffleU32x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1);
133+
Id EmitCompositeShuffleU32x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
134+
u32 comp2);
135+
Id EmitCompositeShuffleU32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
136+
u32 comp2, u32 comp3);
137+
Id EmitCompositeConstructF16x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2);
138+
Id EmitCompositeConstructF16x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3);
139+
Id EmitCompositeConstructF16x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4);
135140
Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index);
136141
Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index);
137142
Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index);
138143
Id EmitCompositeInsertF16x2(EmitContext& ctx, Id composite, Id object, u32 index);
139144
Id EmitCompositeInsertF16x3(EmitContext& ctx, Id composite, Id object, u32 index);
140145
Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index);
141-
Id EmitCompositeConstructF32x2(EmitContext& ctx, Id e1, Id e2);
142-
Id EmitCompositeConstructF32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
143-
Id EmitCompositeConstructF32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
146+
Id EmitCompositeShuffleF16x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1);
147+
Id EmitCompositeShuffleF16x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
148+
u32 comp2);
149+
Id EmitCompositeShuffleF16x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
150+
u32 comp2, u32 comp3);
151+
Id EmitCompositeConstructF32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2);
152+
Id EmitCompositeConstructF32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3);
153+
Id EmitCompositeConstructF32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4);
144154
Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index);
145155
Id EmitCompositeExtractF32x3(EmitContext& ctx, Id composite, u32 index);
146156
Id EmitCompositeExtractF32x4(EmitContext& ctx, Id composite, u32 index);
147157
Id EmitCompositeInsertF32x2(EmitContext& ctx, Id composite, Id object, u32 index);
148158
Id EmitCompositeInsertF32x3(EmitContext& ctx, Id composite, Id object, u32 index);
149159
Id EmitCompositeInsertF32x4(EmitContext& ctx, Id composite, Id object, u32 index);
160+
Id EmitCompositeShuffleF32x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1);
161+
Id EmitCompositeShuffleF32x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
162+
u32 comp2);
163+
Id EmitCompositeShuffleF32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
164+
u32 comp2, u32 comp3);
150165
void EmitCompositeConstructF64x2(EmitContext& ctx);
151166
void EmitCompositeConstructF64x3(EmitContext& ctx);
152167
void EmitCompositeConstructF64x4(EmitContext& ctx);
@@ -156,6 +171,11 @@ void EmitCompositeExtractF64x4(EmitContext& ctx);
156171
Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index);
157172
Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index);
158173
Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index);
174+
Id EmitCompositeShuffleF64x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1);
175+
Id EmitCompositeShuffleF64x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
176+
u32 comp2);
177+
Id EmitCompositeShuffleF64x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
178+
u32 comp2, u32 comp3);
159179
Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value);
160180
Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value);
161181
Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value);

‎src/shader_recompiler/frontend/translate/export.cpp

Lines changed: 13 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -25,34 +25,28 @@ void Translator::EmitExport(const GcnInst& inst) {
2525
IR::VectorReg(inst.src[3].code),
2626
};
2727

28-
const auto swizzle = [&](u32 comp) {
28+
const auto set_attribute = [&](u32 comp, IR::F32 value) {
2929
if (!IR::IsMrt(attrib)) {
30-
return comp;
30+
ir.SetAttribute(attrib, value, comp);
31+
return;
3132
}
3233
const u32 index = u32(attrib) - u32(IR::Attribute::RenderTarget0);
33-
switch (runtime_info.fs_info.color_buffers[index].mrt_swizzle) {
34-
case MrtSwizzle::Identity:
35-
return comp;
36-
case MrtSwizzle::Alt:
37-
static constexpr std::array<u32, 4> AltSwizzle = {2, 1, 0, 3};
38-
return AltSwizzle[comp];
39-
case MrtSwizzle::Reverse:
40-
static constexpr std::array<u32, 4> RevSwizzle = {3, 2, 1, 0};
41-
return RevSwizzle[comp];
42-
case MrtSwizzle::ReverseAlt:
43-
static constexpr std::array<u32, 4> AltRevSwizzle = {3, 0, 1, 2};
44-
return AltRevSwizzle[comp];
45-
default:
46-
UNREACHABLE();
34+
const auto [r, g, b, a] = runtime_info.fs_info.color_buffers[index].swizzle;
35+
const std::array swizzle_array = {r, g, b, a};
36+
const auto swizzled_comp = swizzle_array[comp];
37+
if (u32(swizzled_comp) < u32(AmdGpu::CompSwizzle::Red)) {
38+
ir.SetAttribute(attrib, value, comp);
39+
return;
4740
}
41+
ir.SetAttribute(attrib, value, u32(swizzled_comp) - u32(AmdGpu::CompSwizzle::Red));
4842
};
4943

5044
const auto unpack = [&](u32 idx) {
5145
const IR::Value value = ir.UnpackHalf2x16(ir.GetVectorReg(vsrc[idx]));
5246
const IR::F32 r = IR::F32{ir.CompositeExtract(value, 0)};
5347
const IR::F32 g = IR::F32{ir.CompositeExtract(value, 1)};
54-
ir.SetAttribute(attrib, r, swizzle(idx * 2));
55-
ir.SetAttribute(attrib, g, swizzle(idx * 2 + 1));
48+
set_attribute(idx * 2, r);
49+
set_attribute(idx * 2 + 1, g);
5650
};
5751

5852
// Components are float16 packed into a VGPR
@@ -73,7 +67,7 @@ void Translator::EmitExport(const GcnInst& inst) {
7367
continue;
7468
}
7569
const IR::F32 comp = ir.GetVectorReg<IR::F32>(vsrc[i]);
76-
ir.SetAttribute(attrib, comp, swizzle(i));
70+
set_attribute(i, comp);
7771
}
7872
}
7973
if (IR::IsMrt(attrib)) {

‎src/shader_recompiler/frontend/translate/translate.cpp

Lines changed: 6 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
#include "shader_recompiler/info.h"
1111
#include "shader_recompiler/ir/attribute.h"
1212
#include "shader_recompiler/ir/reg.h"
13+
#include "shader_recompiler/ir/reinterpret.h"
1314
#include "shader_recompiler/runtime_info.h"
1415
#include "video_core/amdgpu/resource.h"
1516
#include "video_core/amdgpu/types.h"
@@ -475,26 +476,12 @@ void Translator::EmitFetch(const GcnInst& inst) {
475476

476477
// Read the V# of the attribute to figure out component number and type.
477478
const auto buffer = info.ReadUdReg<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
479+
const auto values =
480+
ir.CompositeConstruct(ir.GetAttribute(attr, 0), ir.GetAttribute(attr, 1),
481+
ir.GetAttribute(attr, 2), ir.GetAttribute(attr, 3));
482+
const auto swizzled = ApplySwizzle(ir, values, buffer.DstSelect());
478483
for (u32 i = 0; i < 4; i++) {
479-
const IR::F32 comp = [&] {
480-
switch (buffer.GetSwizzle(i)) {
481-
case AmdGpu::CompSwizzle::One:
482-
return ir.Imm32(1.f);
483-
case AmdGpu::CompSwizzle::Zero:
484-
return ir.Imm32(0.f);
485-
case AmdGpu::CompSwizzle::Red:
486-
return ir.GetAttribute(attr, 0);
487-
case AmdGpu::CompSwizzle::Green:
488-
return ir.GetAttribute(attr, 1);
489-
case AmdGpu::CompSwizzle::Blue:
490-
return ir.GetAttribute(attr, 2);
491-
case AmdGpu::CompSwizzle::Alpha:
492-
return ir.GetAttribute(attr, 3);
493-
default:
494-
UNREACHABLE();
495-
}
496-
}();
497-
ir.SetVectorReg(dst_reg++, comp);
484+
ir.SetVectorReg(dst_reg++, IR::F32{ir.CompositeExtract(swizzled, i)});
498485
}
499486

500487
// In case of programmable step rates we need to fallback to instance data pulling in

‎src/shader_recompiler/frontend/translate/vector_memory.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ void Translator::BUFFER_STORE_FORMAT(u32 num_dwords, const GcnInst& inst) {
326326

327327
const IR::VectorReg src_reg{inst.src[1].code};
328328

329-
std::array<IR::Value, 4> comps{};
329+
std::array<IR::F32, 4> comps{};
330330
for (u32 i = 0; i < num_dwords; i++) {
331331
comps[i] = ir.GetVectorReg<IR::F32>(src_reg + i);
332332
}
@@ -424,7 +424,7 @@ void Translator::IMAGE_LOAD(bool has_mip, const GcnInst& inst) {
424424
if (((mimg.dmask >> i) & 1) == 0) {
425425
continue;
426426
}
427-
IR::U32 value = IR::U32{ir.CompositeExtract(texel, i)};
427+
IR::F32 value = IR::F32{ir.CompositeExtract(texel, i)};
428428
ir.SetVectorReg(dest_reg++, value);
429429
}
430430
}

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