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ASoC: SOF: ABI: Split ABI headers and update to latest FW ABI.
Copy FW IPC headers to include/sound/sof/. Copy FW userspace ABI headers to include/uapi/sound/sof/. Fix various include guards and comments for kernel. Signed-off-by: Liam Girdwood <[email protected]>
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‎include/sound/sof.h

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#include <linux/pci.h>
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#include <sound/soc.h>
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#include <sound/soc-acpi.h>
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#include <uapi/sound/sof-ipc.h>
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struct snd_sof_dsp_ops;
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‎include/sound/sof/control.h

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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note)) OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2018 Intel Corporation. All rights reserved.
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*/
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#ifndef __INCLUDE_SOUND_SOF_CONTROL_H__
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#define __INCLUDE_SOUND_SOF_CONTROL_H__
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#include <uapi/sound/sof/header.h>
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#include <sound/sof/header.h>
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/*
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* Component Mixers and Controls
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*/
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/* channel positions - uses same values as ALSA */
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enum sof_ipc_chmap {
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SOF_CHMAP_UNKNOWN = 0,
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SOF_CHMAP_NA, /**< N/A, silent */
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SOF_CHMAP_MONO, /**< mono stream */
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SOF_CHMAP_FL, /**< front left */
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SOF_CHMAP_FR, /**< front right */
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SOF_CHMAP_RL, /**< rear left */
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SOF_CHMAP_RR, /**< rear right */
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SOF_CHMAP_FC, /**< front centre */
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SOF_CHMAP_LFE, /**< LFE */
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SOF_CHMAP_SL, /**< side left */
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SOF_CHMAP_SR, /**< side right */
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SOF_CHMAP_RC, /**< rear centre */
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SOF_CHMAP_FLC, /**< front left centre */
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SOF_CHMAP_FRC, /**< front right centre */
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SOF_CHMAP_RLC, /**< rear left centre */
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SOF_CHMAP_RRC, /**< rear right centre */
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SOF_CHMAP_FLW, /**< front left wide */
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SOF_CHMAP_FRW, /**< front right wide */
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SOF_CHMAP_FLH, /**< front left high */
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SOF_CHMAP_FCH, /**< front centre high */
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SOF_CHMAP_FRH, /**< front right high */
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SOF_CHMAP_TC, /**< top centre */
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SOF_CHMAP_TFL, /**< top front left */
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SOF_CHMAP_TFR, /**< top front right */
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SOF_CHMAP_TFC, /**< top front centre */
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SOF_CHMAP_TRL, /**< top rear left */
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SOF_CHMAP_TRR, /**< top rear right */
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SOF_CHMAP_TRC, /**< top rear centre */
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SOF_CHMAP_TFLC, /**< top front left centre */
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SOF_CHMAP_TFRC, /**< top front right centre */
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SOF_CHMAP_TSL, /**< top side left */
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SOF_CHMAP_TSR, /**< top side right */
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SOF_CHMAP_LLFE, /**< left LFE */
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SOF_CHMAP_RLFE, /**< right LFE */
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SOF_CHMAP_BC, /**< bottom centre */
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SOF_CHMAP_BLC, /**< bottom left centre */
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SOF_CHMAP_BRC, /**< bottom right centre */
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SOF_CHMAP_LAST = SOF_CHMAP_BRC,
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};
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/* control data type and direction */
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enum sof_ipc_ctrl_type {
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/* per channel data - uses struct sof_ipc_ctrl_value_chan */
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SOF_CTRL_TYPE_VALUE_CHAN_GET = 0,
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SOF_CTRL_TYPE_VALUE_CHAN_SET,
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/* component data - uses struct sof_ipc_ctrl_value_comp */
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SOF_CTRL_TYPE_VALUE_COMP_GET,
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SOF_CTRL_TYPE_VALUE_COMP_SET,
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/* bespoke data - struct struct sof_abi_hdr */
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SOF_CTRL_TYPE_DATA_GET,
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SOF_CTRL_TYPE_DATA_SET,
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};
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/* control command type */
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enum sof_ipc_ctrl_cmd {
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SOF_CTRL_CMD_VOLUME = 0, /**< maps to ALSA volume style controls */
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SOF_CTRL_CMD_ENUM, /**< maps to ALSA enum style controls */
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SOF_CTRL_CMD_SWITCH, /**< maps to ALSA switch style controls */
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SOF_CTRL_CMD_BINARY, /**< maps to ALSA binary style controls */
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};
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/* generic channel mapped value data */
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struct sof_ipc_ctrl_value_chan {
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uint32_t channel; /**< channel map - enum sof_ipc_chmap */
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uint32_t value;
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} __packed;
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/* generic component mapped value data */
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struct sof_ipc_ctrl_value_comp {
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uint32_t index; /**< component source/sink/control index in control */
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union {
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uint32_t uvalue;
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int32_t svalue;
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};
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} __packed;
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/* generic control data */
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struct sof_ipc_ctrl_data {
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struct sof_ipc_reply rhdr;
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uint32_t comp_id;
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/* control access and data type */
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uint32_t type; /**< enum sof_ipc_ctrl_type */
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uint32_t cmd; /**< enum sof_ipc_ctrl_cmd */
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uint32_t index; /**< control index for comps > 1 control */
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/* control data - can either be appended or DMAed from host */
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struct sof_ipc_host_buffer buffer;
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uint32_t num_elems; /**< in array elems or bytes */
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/* reserved for future use */
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uint32_t reserved[8];
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/* control data - add new types if needed */
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union {
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/* channel values can be used by volume type controls */
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struct sof_ipc_ctrl_value_chan chanv[0];
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/* component values used by routing controls like mux, mixer */
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struct sof_ipc_ctrl_value_comp compv[0];
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/* data can be used by binary controls */
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struct sof_abi_hdr data[0];
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};
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} __packed;
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#endif

‎include/sound/sof/dai-intel.h

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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note)) OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2018 Intel Corporation. All rights reserved.
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*/
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#ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__
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#define __INCLUDE_SOUND_SOF_DAI_INTEL_H__
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#include <sound/sof/header.h>
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/* ssc1: TINTE */
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#define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0)
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/* ssc1: PINTE */
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#define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1)
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/* ssc2: SMTATF */
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#define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2)
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/* ssc2: MMRATF */
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#define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3)
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/* ssc2: PSPSTWFDFD */
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#define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4)
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/* ssc2: PSPSRWFDFD */
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#define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5)
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/* here is the possibility to define others aux macros */
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#define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38
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#define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31
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/* SSP clocks control settings
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*
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* Macros for clks_control field in sof_ipc_dai_ssp_params struct.
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*/
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/* mclk 0 disable */
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#define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0)
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/* mclk 1 disable */
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#define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1)
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/* mclk keep active */
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#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2)
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/* bclk keep active */
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#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3)
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/* fs keep active */
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#define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4)
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/* bclk idle */
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#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
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/* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
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struct sof_ipc_dai_ssp_params {
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uint16_t reserved1;
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uint16_t mclk_id;
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uint32_t mclk_rate; /* mclk frequency in Hz */
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uint32_t fsync_rate; /* fsync frequency in Hz */
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uint32_t bclk_rate; /* bclk frequency in Hz */
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/* TDM */
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uint32_t tdm_slots;
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uint32_t rx_slots;
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uint32_t tx_slots;
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/* data */
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uint32_t sample_valid_bits;
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uint16_t tdm_slot_width;
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uint16_t reserved2; /* alignment */
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/* MCLK */
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uint32_t mclk_direction;
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uint16_t frame_pulse_width;
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uint16_t tdm_per_slot_padding_flag;
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uint32_t clks_control;
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uint32_t quirks;
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} __packed;
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/* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
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struct sof_ipc_dai_hda_params {
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struct sof_ipc_hdr hdr;
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/* TODO */
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} __packed;
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/* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
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/* This struct is defined per 2ch PDM controller available in the platform.
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* Normally it is sufficient to set the used microphone specific enables to 1
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* and keep other parameters as zero. The customizations are:
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*
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* 1. If a device mixes different microphones types with different polarity
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* and/or the absolute polarity matters the PCM signal from a microphone
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* can be inverted with the controls.
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*
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* 2. If the microphones in a stereo pair do not appear in captured stream
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* in desired order due to board schematics choises they can be swapped with
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* the clk_edge parameter.
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*
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* 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
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* that delays the sampling time of data by half cycles of DMIC source clock
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* can be tried for improvement. However there is no guarantee for this to fix
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* data integrity problems.
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*/
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struct sof_ipc_dai_dmic_pdm_ctrl {
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uint16_t id; /**< PDM controller ID */
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uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/
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uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/
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uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */
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uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */
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uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */
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uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */
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uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */
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} __packed;
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/* This struct contains the global settings for all 2ch PDM controllers. The
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* version number used in configuration data is checked vs. version used by
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* device driver src/drivers/dmic.c need to match. It is incremented from
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* initial value 1 if updates done for the to driver would alter the operation
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* of the microhone.
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*
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* Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max)
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* parameters need to be set as defined in microphone data sheet. E.g. clock
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* range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
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* multi-mode capable and there may be denied mic clock frequencies between
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* the modes. In such case set the clock range limits of the desired mode to
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* avoid the driver to set clock to an illegal rate.
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*
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* The duty cycle could be set to 48-52% if not known. Generally these
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* parameters can be altered within data sheet specified limits to match
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* required audio application performance power.
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*
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* The microphone clock needs to be usually about 50-80 times the used audio
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* sample rate. With highest sample rates above 48 kHz this can relaxed
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* somewhat.
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*/
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struct sof_ipc_dai_dmic_params {
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uint32_t driver_ipc_version; /**< Version (1..N) */
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uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */
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uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */
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uint32_t fifo_fs_a; /**< FIFO A sample rate in Hz (8000..96000) */
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uint32_t fifo_fs_b; /**< FIFO B sample rate in Hz (8000..96000) */
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uint16_t fifo_bits_a; /**< FIFO A word length (16 or 32) */
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uint16_t fifo_bits_b; /**< FIFO B word length (16 or 32) */
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uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */
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uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */
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uint32_t num_pdm_active; /**< Number of active pdm controllers */
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/* reserved for future use */
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uint32_t reserved[8];
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/**< variable number of pdm controller config */
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struct sof_ipc_dai_dmic_pdm_ctrl pdm[0];
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} __packed;
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#endif

‎include/sound/sof/dai.h

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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note)) OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2018 Intel Corporation. All rights reserved.
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*/
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#ifndef __INCLUDE_SOUND_SOF_DAI_H__
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#define __INCLUDE_SOUND_SOF_DAI_H__
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#include <sound/sof/header.h>
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#include <sound/sof/dai-intel.h>
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/*
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* DAI Configuration.
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*
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* Each different DAI type will have it's own structure and IPC cmd.
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*/
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#define SOF_DAI_FMT_I2S 1 /**< I2S mode */
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#define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */
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#define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */
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#define SOF_DAI_FMT_DSP_A 4 /**< L data MSB after FRM LRC */
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#define SOF_DAI_FMT_DSP_B 5 /**< L data MSB during FRM LRC */
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#define SOF_DAI_FMT_PDM 6 /**< Pulse density modulation */
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#define SOF_DAI_FMT_CONT (1 << 4) /**< continuous clock */
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#define SOF_DAI_FMT_GATED (0 << 4) /**< clock is gated */
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#define SOF_DAI_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */
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#define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
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#define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
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#define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
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#define SOF_DAI_FMT_CBM_CFM (0 << 12) /**< codec clk & FRM master */
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#define SOF_DAI_FMT_CBS_CFM (2 << 12) /**< codec clk slave & FRM master */
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#define SOF_DAI_FMT_CBM_CFS (3 << 12) /**< codec clk master & frame slave */
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#define SOF_DAI_FMT_CBS_CFS (4 << 12) /**< codec clk & FRM slave */
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#define SOF_DAI_FMT_FORMAT_MASK 0x000f
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#define SOF_DAI_FMT_CLOCK_MASK 0x00f0
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#define SOF_DAI_FMT_INV_MASK 0x0f00
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#define SOF_DAI_FMT_MASTER_MASK 0xf000
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/** \brief Types of DAI */
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enum sof_ipc_dai_type {
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SOF_DAI_INTEL_NONE = 0, /**< None */
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SOF_DAI_INTEL_SSP, /**< Intel SSP */
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SOF_DAI_INTEL_DMIC, /**< Intel DMIC */
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SOF_DAI_INTEL_HDA, /**< Intel HD/A */
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};
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/* general purpose DAI configuration */
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struct sof_ipc_dai_config {
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struct sof_ipc_hdr hdr;
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uint32_t type; /**< DAI type - enum sof_ipc_dai_type */
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uint32_t dai_index; /**< index of this type dai */
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/* physical protocol and clocking */
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uint16_t format; /**< SOF_DAI_FMT_ */
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uint16_t reserved16; /**< alignment */
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/* reserved for future use */
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uint32_t reserved[8];
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/* HW specific data */
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union {
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struct sof_ipc_dai_ssp_params ssp;
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struct sof_ipc_dai_dmic_params dmic;
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struct sof_ipc_dai_hda_params hda;
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};
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} __packed;
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#endif

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