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| 1 | +// Copyright (c) Facebook, Inc. and its affiliates. All Rights Reserved. |
| 2 | +#include <ATen/ATen.h> |
| 3 | +#include <ATen/cuda/CUDAContext.h> |
| 4 | + |
| 5 | +#include <THC/THC.h> |
| 6 | +#include <THC/THCDeviceUtils.cuh> |
| 7 | + |
| 8 | +#include <vector> |
| 9 | +#include <iostream> |
| 10 | + |
| 11 | +int const threadsPerBlock = sizeof(unsigned long long) * 8; |
| 12 | + |
| 13 | +__device__ inline float devIoU(float const * const a, float const * const b) { |
| 14 | + if (a[5] != b[5]) { |
| 15 | + return 0.0; |
| 16 | + } |
| 17 | + float left = max(a[0], b[0]), right = min(a[2], b[2]); |
| 18 | + float top = max(a[1], b[1]), bottom = min(a[3], b[3]); |
| 19 | + float width = max(right - left + 1, 0.f), height = max(bottom - top + 1, 0.f); |
| 20 | + float interS = width * height; |
| 21 | + float Sa = (a[2] - a[0] + 1) * (a[3] - a[1] + 1); |
| 22 | + float Sb = (b[2] - b[0] + 1) * (b[3] - b[1] + 1); |
| 23 | + return interS / (Sa + Sb - interS); |
| 24 | +} |
| 25 | + |
| 26 | +__global__ void ml_nms_kernel(const int n_boxes, const float nms_overlap_thresh, |
| 27 | + const float *dev_boxes, unsigned long long *dev_mask) { |
| 28 | + const int row_start = blockIdx.y; |
| 29 | + const int col_start = blockIdx.x; |
| 30 | + |
| 31 | + // if (row_start > col_start) return; |
| 32 | + |
| 33 | + const int row_size = |
| 34 | + min(n_boxes - row_start * threadsPerBlock, threadsPerBlock); |
| 35 | + const int col_size = |
| 36 | + min(n_boxes - col_start * threadsPerBlock, threadsPerBlock); |
| 37 | + |
| 38 | + __shared__ float block_boxes[threadsPerBlock * 6]; |
| 39 | + if (threadIdx.x < col_size) { |
| 40 | + block_boxes[threadIdx.x * 6 + 0] = |
| 41 | + dev_boxes[(threadsPerBlock * col_start + threadIdx.x) * 6 + 0]; |
| 42 | + block_boxes[threadIdx.x * 6 + 1] = |
| 43 | + dev_boxes[(threadsPerBlock * col_start + threadIdx.x) * 6 + 1]; |
| 44 | + block_boxes[threadIdx.x * 6 + 2] = |
| 45 | + dev_boxes[(threadsPerBlock * col_start + threadIdx.x) * 6 + 2]; |
| 46 | + block_boxes[threadIdx.x * 6 + 3] = |
| 47 | + dev_boxes[(threadsPerBlock * col_start + threadIdx.x) * 6 + 3]; |
| 48 | + block_boxes[threadIdx.x * 6 + 4] = |
| 49 | + dev_boxes[(threadsPerBlock * col_start + threadIdx.x) * 6 + 4]; |
| 50 | + block_boxes[threadIdx.x * 6 + 5] = |
| 51 | + dev_boxes[(threadsPerBlock * col_start + threadIdx.x) * 6 + 5]; |
| 52 | + } |
| 53 | + __syncthreads(); |
| 54 | + |
| 55 | + if (threadIdx.x < row_size) { |
| 56 | + const int cur_box_idx = threadsPerBlock * row_start + threadIdx.x; |
| 57 | + const float *cur_box = dev_boxes + cur_box_idx * 6; |
| 58 | + int i = 0; |
| 59 | + unsigned long long t = 0; |
| 60 | + int start = 0; |
| 61 | + if (row_start == col_start) { |
| 62 | + start = threadIdx.x + 1; |
| 63 | + } |
| 64 | + for (i = start; i < col_size; i++) { |
| 65 | + if (devIoU(cur_box, block_boxes + i * 6) > nms_overlap_thresh) { |
| 66 | + t |= 1ULL << i; |
| 67 | + } |
| 68 | + } |
| 69 | + const int col_blocks = THCCeilDiv(n_boxes, threadsPerBlock); |
| 70 | + dev_mask[cur_box_idx * col_blocks + col_start] = t; |
| 71 | + } |
| 72 | +} |
| 73 | + |
| 74 | +// boxes is a N x 6 tensor |
| 75 | +at::Tensor ml_nms_cuda(const at::Tensor boxes, float nms_overlap_thresh) { |
| 76 | + using scalar_t = float; |
| 77 | + AT_ASSERTM(boxes.type().is_cuda(), "boxes must be a CUDA tensor"); |
| 78 | + auto scores = boxes.select(1, 4); |
| 79 | + auto order_t = std::get<1>(scores.sort(0, /* descending=*/true)); |
| 80 | + auto boxes_sorted = boxes.index_select(0, order_t); |
| 81 | + |
| 82 | + int boxes_num = boxes.size(0); |
| 83 | + |
| 84 | + const int col_blocks = THCCeilDiv(boxes_num, threadsPerBlock); |
| 85 | + |
| 86 | + scalar_t* boxes_dev = boxes_sorted.data<scalar_t>(); |
| 87 | + |
| 88 | + THCState *state = at::globalContext().lazyInitCUDA(); // TODO replace with getTHCState |
| 89 | + |
| 90 | + unsigned long long* mask_dev = NULL; |
| 91 | + //THCudaCheck(THCudaMalloc(state, (void**) &mask_dev, |
| 92 | + // boxes_num * col_blocks * sizeof(unsigned long long))); |
| 93 | + |
| 94 | + mask_dev = (unsigned long long*) THCudaMalloc(state, boxes_num * col_blocks * sizeof(unsigned long long)); |
| 95 | + |
| 96 | + dim3 blocks(THCCeilDiv(boxes_num, threadsPerBlock), |
| 97 | + THCCeilDiv(boxes_num, threadsPerBlock)); |
| 98 | + dim3 threads(threadsPerBlock); |
| 99 | + ml_nms_kernel<<<blocks, threads>>>(boxes_num, |
| 100 | + nms_overlap_thresh, |
| 101 | + boxes_dev, |
| 102 | + mask_dev); |
| 103 | + |
| 104 | + std::vector<unsigned long long> mask_host(boxes_num * col_blocks); |
| 105 | + THCudaCheck(cudaMemcpy(&mask_host[0], |
| 106 | + mask_dev, |
| 107 | + sizeof(unsigned long long) * boxes_num * col_blocks, |
| 108 | + cudaMemcpyDeviceToHost)); |
| 109 | + |
| 110 | + std::vector<unsigned long long> remv(col_blocks); |
| 111 | + memset(&remv[0], 0, sizeof(unsigned long long) * col_blocks); |
| 112 | + |
| 113 | + at::Tensor keep = at::empty({boxes_num}, boxes.options().dtype(at::kLong).device(at::kCPU)); |
| 114 | + int64_t* keep_out = keep.data<int64_t>(); |
| 115 | + |
| 116 | + int num_to_keep = 0; |
| 117 | + for (int i = 0; i < boxes_num; i++) { |
| 118 | + int nblock = i / threadsPerBlock; |
| 119 | + int inblock = i % threadsPerBlock; |
| 120 | + |
| 121 | + if (!(remv[nblock] & (1ULL << inblock))) { |
| 122 | + keep_out[num_to_keep++] = i; |
| 123 | + unsigned long long *p = &mask_host[0] + i * col_blocks; |
| 124 | + for (int j = nblock; j < col_blocks; j++) { |
| 125 | + remv[j] |= p[j]; |
| 126 | + } |
| 127 | + } |
| 128 | + } |
| 129 | + |
| 130 | + THCudaFree(state, mask_dev); |
| 131 | + // TODO improve this part |
| 132 | + return std::get<0>(order_t.index({ |
| 133 | + keep.narrow(/*dim=*/0, /*start=*/0, /*length=*/num_to_keep).to( |
| 134 | + order_t.device(), keep.scalar_type()) |
| 135 | + }).sort(0, false)); |
| 136 | +} |
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