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phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
Add register sequences for PCIe + SGMII PHY multilink configuration. This has been validated on TI J7 platforms. Signed-off-by: Swapnil Jakhade <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/cadence/phy-cadence-sierra.c

Lines changed: 139 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
#include <dt-bindings/phy/phy-cadence.h>
2525

2626
#define NUM_SSC_MODE 3
27-
#define NUM_PHY_TYPE 4
27+
#define NUM_PHY_TYPE 5
2828

2929
/* PHY register offsets */
3030
#define SIERRA_COMMON_CDB_OFFSET 0x0
@@ -46,7 +46,9 @@
4646
#define SIERRA_CMN_REFRCV_PREG 0x98
4747
#define SIERRA_CMN_REFRCV1_PREG 0xB8
4848
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
49+
#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3
4950
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
51+
#define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE
5052
#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
5153
#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
5254

@@ -74,6 +76,7 @@
7476
#define SIERRA_PSC_RX_A1_PREG 0x031
7577
#define SIERRA_PSC_RX_A2_PREG 0x032
7678
#define SIERRA_PSC_RX_A3_PREG 0x033
79+
#define SIERRA_PLLCTRL_FBDIV_MODE01_PREG 0x039
7780
#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
7881
#define SIERRA_PLLCTRL_GEN_A_PREG 0x03B
7982
#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
@@ -305,6 +308,7 @@ enum cdns_sierra_phy_type {
305308
TYPE_NONE,
306309
TYPE_PCIE,
307310
TYPE_USB,
311+
TYPE_SGMII,
308312
TYPE_QSGMII
309313
};
310314

@@ -929,6 +933,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
929933
case PHY_TYPE_USB3:
930934
inst->phy_type = TYPE_USB;
931935
break;
936+
case PHY_TYPE_SGMII:
937+
inst->phy_type = TYPE_SGMII;
938+
break;
932939
case PHY_TYPE_QSGMII:
933940
inst->phy_type = TYPE_QSGMII;
934941
break;
@@ -1316,7 +1323,7 @@ static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
13161323
}
13171324
}
13181325

1319-
if (phy_t1 == TYPE_QSGMII)
1326+
if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII)
13201327
reset_control_deassert(sp->phys[node].lnk_rst);
13211328
}
13221329

@@ -1514,6 +1521,71 @@ static void cdns_sierra_phy_remove(struct platform_device *pdev)
15141521
cdns_sierra_clk_unregister(phy);
15151522
}
15161523

1524+
/* SGMII PHY PMA lane configuration */
1525+
static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = {
1526+
{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
1527+
};
1528+
1529+
static struct cdns_sierra_vals sgmii_phy_pma_ln_vals = {
1530+
.reg_pairs = sgmii_phy_pma_ln_regs,
1531+
.num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs),
1532+
};
1533+
1534+
/* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */
1535+
static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = {
1536+
{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
1537+
{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
1538+
{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},
1539+
{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
1540+
{0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
1541+
};
1542+
1543+
static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = {
1544+
{0x688E, SIERRA_DET_STANDEC_D_PREG},
1545+
{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1546+
{0x0FFE, SIERRA_PSC_RX_A0_PREG},
1547+
{0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
1548+
{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
1549+
{0x0003, SIERRA_PLLCTRL_GEN_A_PREG},
1550+
{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
1551+
{0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG },
1552+
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1553+
{0x9702, SIERRA_DRVCTRL_BOOST_PREG},
1554+
{0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1555+
{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1556+
{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
1557+
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1558+
{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
1559+
{0x0186, SIERRA_DEQ_GLUT0},
1560+
{0x0186, SIERRA_DEQ_GLUT1},
1561+
{0x0186, SIERRA_DEQ_GLUT2},
1562+
{0x0186, SIERRA_DEQ_GLUT3},
1563+
{0x0186, SIERRA_DEQ_GLUT4},
1564+
{0x0861, SIERRA_DEQ_ALUT0},
1565+
{0x07E0, SIERRA_DEQ_ALUT1},
1566+
{0x079E, SIERRA_DEQ_ALUT2},
1567+
{0x071D, SIERRA_DEQ_ALUT3},
1568+
{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
1569+
{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1570+
{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1571+
{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
1572+
{0x0033, SIERRA_DEQ_PICTRL_PREG},
1573+
{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1574+
{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
1575+
{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
1576+
{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
1577+
};
1578+
1579+
static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = {
1580+
.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs,
1581+
.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs),
1582+
};
1583+
1584+
static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = {
1585+
.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs,
1586+
.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs),
1587+
};
1588+
15171589
/* QSGMII PHY PMA lane configuration */
15181590
static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
15191591
{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
@@ -2340,6 +2412,11 @@ static const struct cdns_sierra_data cdns_map_sierra = {
23402412
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
23412413
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
23422414
},
2415+
[TYPE_SGMII] = {
2416+
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2417+
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2418+
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2419+
},
23432420
[TYPE_QSGMII] = {
23442421
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
23452422
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
@@ -2354,6 +2431,11 @@ static const struct cdns_sierra_data cdns_map_sierra = {
23542431
[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
23552432
[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
23562433
},
2434+
[TYPE_SGMII] = {
2435+
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2436+
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2437+
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2438+
},
23572439
[TYPE_QSGMII] = {
23582440
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
23592441
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
@@ -2365,6 +2447,13 @@ static const struct cdns_sierra_data cdns_map_sierra = {
23652447
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
23662448
},
23672449
},
2450+
[TYPE_SGMII] = {
2451+
[TYPE_PCIE] = {
2452+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2453+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2454+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2455+
},
2456+
},
23682457
[TYPE_QSGMII] = {
23692458
[TYPE_PCIE] = {
23702459
[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
@@ -2380,6 +2469,11 @@ static const struct cdns_sierra_data cdns_map_sierra = {
23802469
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
23812470
[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
23822471
},
2472+
[TYPE_SGMII] = {
2473+
[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
2474+
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
2475+
[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
2476+
},
23832477
[TYPE_QSGMII] = {
23842478
[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
23852479
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
@@ -2391,6 +2485,13 @@ static const struct cdns_sierra_data cdns_map_sierra = {
23912485
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
23922486
},
23932487
},
2488+
[TYPE_SGMII] = {
2489+
[TYPE_PCIE] = {
2490+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2491+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2492+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2493+
},
2494+
},
23942495
[TYPE_QSGMII] = {
23952496
[TYPE_PCIE] = {
23962497
[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
@@ -2412,6 +2513,11 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
24122513
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
24132514
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
24142515
},
2516+
[TYPE_SGMII] = {
2517+
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2518+
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2519+
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2520+
},
24152521
[TYPE_QSGMII] = {
24162522
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
24172523
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
@@ -2420,6 +2526,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
24202526
},
24212527
},
24222528
.phy_pma_ln_vals = {
2529+
[TYPE_SGMII] = {
2530+
[TYPE_PCIE] = {
2531+
[NO_SSC] = &sgmii_phy_pma_ln_vals,
2532+
[EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals,
2533+
[INTERNAL_SSC] = &sgmii_phy_pma_ln_vals,
2534+
},
2535+
},
24232536
[TYPE_QSGMII] = {
24242537
[TYPE_PCIE] = {
24252538
[NO_SSC] = &qsgmii_phy_pma_ln_vals,
@@ -2435,6 +2548,11 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
24352548
[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
24362549
[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
24372550
},
2551+
[TYPE_SGMII] = {
2552+
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2553+
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2554+
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2555+
},
24382556
[TYPE_QSGMII] = {
24392557
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
24402558
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
@@ -2446,6 +2564,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
24462564
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
24472565
},
24482566
},
2567+
[TYPE_SGMII] = {
2568+
[TYPE_PCIE] = {
2569+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2570+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2571+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2572+
},
2573+
},
24492574
[TYPE_QSGMII] = {
24502575
[TYPE_PCIE] = {
24512576
[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
@@ -2461,6 +2586,11 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
24612586
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
24622587
[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
24632588
},
2589+
[TYPE_SGMII] = {
2590+
[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
2591+
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
2592+
[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
2593+
},
24642594
[TYPE_QSGMII] = {
24652595
[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
24662596
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
@@ -2472,6 +2602,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
24722602
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
24732603
},
24742604
},
2605+
[TYPE_SGMII] = {
2606+
[TYPE_PCIE] = {
2607+
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2608+
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2609+
[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2610+
},
2611+
},
24752612
[TYPE_QSGMII] = {
24762613
[TYPE_PCIE] = {
24772614
[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,

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