Generate const binding files with preprocessed headers

Each unicorn/*.h is preprocessed in bindings/tmp/*.h to expand C macro,
then const_generator.py extracts enum from these files.

unicorn.h was adapted by using enum for some defines (because they disapear
in expanded headers)

With preprocessed headers, all <target>.h files are include in tmp/unicorn.h
so unicorn_const.* files contains enum of all targets.
<target>_const.* are kept for compatibility.

Author: jbcayrou

.gitignore

@@ -69,6 +69,7 @@ bindings/python/unicorn/include/
 bindings/python/MANIFEST
 bindings/rust/target/
 bindings/rust/Cargo.lock
+bindings/tmp/
 config.log
 
 

bindings/Makefile

@@ -16,17 +16,34 @@ else
 ENV_VARS = LD_LIBRARY_PATH=../ DYLD_LIBRARY_PATH=../ LIBUNICORN_PATH=$(TRAVIS_BUILD_DIR)
 endif
 
+TEMPDIR = tmp
+
+HEADERS = $(wildcard ../include/unicorn/*.h)
+HEADERS_DIR = ../include/unicorn
+HEADERS_PREPROC_DIR = $(TEMPDIR)
+HEADERS_PREPROC  := $(HEADERS:$(HEADERS_DIR)/%.h=$(HEADERS_PREPROC_DIR)/%.h)
 
 .PHONY: build install python c clean check test
 
-build:
+
+build: $(TEMPDIR) $(HEADERS_PREPROC)
 	$(MAKE) -C python gen_const
 	$(MAKE) -C go gen_const
 	$(MAKE) -C java gen_const
 	$(MAKE) -C ruby gen_const
 	python const_generator.py dotnet
 	python const_generator.py pascal
 
+tmp_headers: $(TEMPDIR) $(HEADERS_PREPROC)
+
+$(TEMPDIR):
+	-mkdir $(TEMPDIR)
+
+$(HEADERS_PREPROC): $(HEADERS_PREPROC_DIR)/%.h : $(HEADERS_DIR)/%.h
+# To generate header file with macro expanded. '-C' to keep comments
+	$(CC) -E -C $< -o $@
+	@echo "Preprocess "$<" in "$@" successfully!"
+
 install: build
 	$(MAKE) -C python install
 	$(MAKE) -C java install
@@ -49,6 +66,6 @@ clean:
 #	rm -rf *.txt
 	$(MAKE) -C python clean
 	$(MAKE) -C java clean
-
+	rm -rf $(TEMPDIR)
 check:
 	make -C python check

bindings/const_generator.py

@@ -4,7 +4,7 @@
 from __future__ import print_function
 import sys, re, os
 
-INCL_DIR = os.path.join('..', 'include', 'unicorn')
+INCL_DIR = os.path.join('.', 'tmp')
 
 include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'm68k.h', 'ppc.h', 'riscv.h', 'unicorn.h' ]
 
@@ -119,6 +119,8 @@
         },
 }
 
+all_arch_prefix = [ template["python"][tmp_target].upper() for tmp_target in include]
+
 # markup for comments to be added to autogen files
 MARKUP = '//>'
 
@@ -129,8 +131,11 @@ def gen(lang):
         prefix = templ[target]
         outfile = open(templ['out_file'] %(prefix), 'wb')   # open as binary prevents windows newlines
         outfile.write((templ['header'] % (prefix)).encode("utf-8"))
+        add_comments = True
+
         if target == 'unicorn.h':
             prefix = ''
+            add_comments = False
         with open(os.path.join(INCL_DIR, target)) as f:
             lines = f.readlines()
 
@@ -139,7 +144,7 @@ def gen(lang):
         for line in lines:
             line = line.strip()
 
-            if line.startswith(MARKUP):  # markup for comments
+            if add_comments and line.startswith(MARKUP):  # markup for comments
                 outfile.write(("\n%s%s%s\n" %(templ['comment_open'], \
                             line.replace(MARKUP, ''), templ['comment_close'])).encode("utf-8"))
                 continue
@@ -170,6 +175,15 @@ def gen(lang):
                     else:
                         rhs = str(count)
 
+                    if prefix == "":
+                        incorrect_prefix = False
+                        for arch in all_arch_prefix:
+                            if f[0].startswith("UC_" + arch):
+                                incorrect_prefix = True
+                                break
+                        if incorrect_prefix:
+                            continue
+
                     lhs = f[0].strip()
                     # evaluate bitshifts in constants e.g. "UC_X86 = 1 << 1"
                     match = re.match(r'(?P<rhs>\s*\d+\s*<<\s*\d+\s*)', rhs)

bindings/dotnet/UnicornManaged/Const/Arm.fs

@@ -120,35 +120,32 @@ module Arm =
     let UC_ARM_REG_S29 = 108
     let UC_ARM_REG_S30 = 109
     let UC_ARM_REG_S31 = 110
-    let UC_ARM_REG_C1_C0_2 = 111
-    let UC_ARM_REG_C13_C0_2 = 112
-    let UC_ARM_REG_C13_C0_3 = 113
-    let UC_ARM_REG_IPSR = 114
-    let UC_ARM_REG_MSP = 115
-    let UC_ARM_REG_PSP = 116
-    let UC_ARM_REG_CONTROL = 117
-    let UC_ARM_REG_IAPSR = 118
-    let UC_ARM_REG_EAPSR = 119
-    let UC_ARM_REG_XPSR = 120
-    let UC_ARM_REG_EPSR = 121
-    let UC_ARM_REG_IEPSR = 122
-    let UC_ARM_REG_PRIMASK = 123
-    let UC_ARM_REG_BASEPRI = 124
-    let UC_ARM_REG_BASEPRI_MAX = 125
-    let UC_ARM_REG_FAULTMASK = 126
-    let UC_ARM_REG_APSR_NZCVQ = 127
-    let UC_ARM_REG_APSR_G = 128
-    let UC_ARM_REG_APSR_NZCVQG = 129
-    let UC_ARM_REG_IAPSR_NZCVQ = 130
-    let UC_ARM_REG_IAPSR_G = 131
-    let UC_ARM_REG_IAPSR_NZCVQG = 132
-    let UC_ARM_REG_EAPSR_NZCVQ = 133
-    let UC_ARM_REG_EAPSR_G = 134
-    let UC_ARM_REG_EAPSR_NZCVQG = 135
-    let UC_ARM_REG_XPSR_NZCVQ = 136
-    let UC_ARM_REG_XPSR_G = 137
-    let UC_ARM_REG_XPSR_NZCVQG = 138
-    let UC_ARM_REG_ENDING = 139
+    let UC_ARM_REG_IPSR = 111
+    let UC_ARM_REG_MSP = 112
+    let UC_ARM_REG_PSP = 113
+    let UC_ARM_REG_CONTROL = 114
+    let UC_ARM_REG_IAPSR = 115
+    let UC_ARM_REG_EAPSR = 116
+    let UC_ARM_REG_XPSR = 117
+    let UC_ARM_REG_EPSR = 118
+    let UC_ARM_REG_IEPSR = 119
+    let UC_ARM_REG_PRIMASK = 120
+    let UC_ARM_REG_BASEPRI = 121
+    let UC_ARM_REG_BASEPRI_MAX = 122
+    let UC_ARM_REG_FAULTMASK = 123
+    let UC_ARM_REG_APSR_NZCVQ = 124
+    let UC_ARM_REG_APSR_G = 125
+    let UC_ARM_REG_APSR_NZCVQG = 126
+    let UC_ARM_REG_IAPSR_NZCVQ = 127
+    let UC_ARM_REG_IAPSR_G = 128
+    let UC_ARM_REG_IAPSR_NZCVQG = 129
+    let UC_ARM_REG_EAPSR_NZCVQ = 130
+    let UC_ARM_REG_EAPSR_G = 131
+    let UC_ARM_REG_EAPSR_NZCVQG = 132
+    let UC_ARM_REG_XPSR_NZCVQ = 133
+    let UC_ARM_REG_XPSR_G = 134
+    let UC_ARM_REG_XPSR_NZCVQG = 135
+    let UC_ARM_REG_ENDING = 136
 
     // alias registers
     let UC_ARM_REG_R13 = 12
@@ -159,3 +156,203 @@ module Arm =
     let UC_ARM_REG_FP = 77
     let UC_ARM_REG_IP = 78
 
+    // CP registers
+    let UC_ARM_REG_ACTLR_EL1 = 2685339649
+    let UC_ARM_REG_ACTLR_EL2 = 2685339681
+    let UC_ARM_REG_ACTLR_EL3 = 2417225857
+    let UC_ARM_REG_AFSR0_EL1 = 2685347968
+    let UC_ARM_REG_AFSR1_EL1 = 2685347969
+    let UC_ARM_REG_AIDR = 2685337615
+    let UC_ARM_REG_AMAIR0 = 2685358464
+    let UC_ARM_REG_AMAIR1 = 2685358465
+    let UC_ARM_REG_ATS12NSOPR = 2685352964
+    let UC_ARM_REG_ATS12NSOPW = 2685352965
+    let UC_ARM_REG_ATS12NSOUR = 2685352966
+    let UC_ARM_REG_ATS12NSOUW = 2685352967
+    let UC_ARM_REG_ATS1CPR = 2685352960
+    let UC_ARM_REG_ATS1CPW = 2685352961
+    let UC_ARM_REG_ATS1CUR = 2685352962
+    let UC_ARM_REG_ATS1CUW = 2685352963
+    let UC_ARM_REG_CBAR = 2685368352
+    let UC_ARM_REG_CCSIDR = 2685337608
+    let UC_ARM_REG_CLIDR = 2685337609
+    let UC_ARM_REG_CNTFRQ = 2685366272
+    let UC_ARM_REG_CNTFRQ_EL0 = 2417221376
+    let UC_ARM_REG_CNTKCTL = 2685366400
+    let UC_ARM_REG_CNTPCT = 2685372160
+    let UC_ARM_REG_CNTPCT_EL0 = 2417221377
+    let UC_ARM_REG_CNTPS_CTL_EL1 = 2417229585
+    let UC_ARM_REG_CNTPS_CVAL_EL1 = 2417229586
+    let UC_ARM_REG_CNTPS_TVAL_EL1 = 2417229584
+    let UC_ARM_REG_CNTP_CTL = 2685366529
+    let UC_ARM_REG_CNTP_CTL_EL0 = 2417221393
+    let UC_ARM_REG_CNTP_CVAL = 2685372176
+    let UC_ARM_REG_CNTP_CVAL_EL0 = 2417221394
+    let UC_ARM_REG_CNTP_TVAL = 2685366528
+    let UC_ARM_REG_CNTP_TVAL_EL0 = 2417221392
+    let UC_ARM_REG_CNTVCT = 2685372168
+    let UC_ARM_REG_CNTVCT_EL0 = 2417221378
+    let UC_ARM_REG_CNTV_CTL = 2685366657
+    let UC_ARM_REG_CNTV_CTL_EL0 = 2417221401
+    let UC_ARM_REG_CNTV_CVAL = 2685372184
+    let UC_ARM_REG_CNTV_CVAL_EL0 = 2417221402
+    let UC_ARM_REG_CNTV_TVAL = 2685366656
+    let UC_ARM_REG_CNTV_TVAL_EL0 = 2417221400
+    let UC_ARM_REG_CONTEXTIDR_EL1 = 2685364225
+    let UC_ARM_REG_CPACR = 2685339650
+    let UC_ARM_REG_CSSELR = 2685337616
+    let UC_ARM_REG_CTR = 2685337601
+    let UC_ARM_REG_CTR_EL0 = 2417219585
+    let UC_ARM_REG_DBGBCR0 = 2685272069
+    let UC_ARM_REG_DBGBCR1 = 2685272197
+    let UC_ARM_REG_DBGBCR2 = 2685272325
+    let UC_ARM_REG_DBGBCR3 = 2685272453
+    let UC_ARM_REG_DBGBCR4 = 2685272581
+    let UC_ARM_REG_DBGBCR5 = 2685272709
+    let UC_ARM_REG_DBGBVR0 = 2685272068
+    let UC_ARM_REG_DBGBVR1 = 2685272196
+    let UC_ARM_REG_DBGBVR2 = 2685272324
+    let UC_ARM_REG_DBGBVR3 = 2685272452
+    let UC_ARM_REG_DBGBVR4 = 2685272580
+    let UC_ARM_REG_DBGBVR5 = 2685272708
+    let UC_ARM_REG_DBGDIDR = 2685272064
+    let UC_ARM_REG_DBGDRAR = 2685304960
+    let UC_ARM_REG_DBGDSAR = 2685305088
+    let UC_ARM_REG_DBGVCR = 2685272960
+    let UC_ARM_REG_DBGVCR32_EL2 = 2417205304
+    let UC_ARM_REG_DBGWCR0 = 2685272071
+    let UC_ARM_REG_DBGWCR1 = 2685272199
+    let UC_ARM_REG_DBGWCR2 = 2685272327
+    let UC_ARM_REG_DBGWCR3 = 2685272455
+    let UC_ARM_REG_DBGWVR0 = 2685272070
+    let UC_ARM_REG_DBGWVR1 = 2685272198
+    let UC_ARM_REG_DBGWVR2 = 2685272326
+    let UC_ARM_REG_DBGWVR3 = 2685272454
+    let UC_ARM_REG_DFAR = 2685349888
+    let UC_ARM_REG_DFSR = 2685347840
+    let UC_ARM_REG_DMB = 2685353221
+    let UC_ARM_REG_DSB = 2685353220
+    let UC_ARM_REG_DTLBIALL = 2685354752
+    let UC_ARM_REG_DTLBIASID = 2685354754
+    let UC_ARM_REG_DTLBIMVA = 2685354753
+    let UC_ARM_REG_ESR_EL1 = 2417214096
+    let UC_ARM_REG_FAR_EL1 = 2417214208
+    let UC_ARM_REG_FCSEIDR = 2685364224
+    let UC_ARM_REG_ID_AFR0 = 2685337731
+    let UC_ARM_REG_ID_DFR0 = 2685337730
+    let UC_ARM_REG_ID_ISAR0 = 2685337856
+    let UC_ARM_REG_ID_ISAR1 = 2685337857
+    let UC_ARM_REG_ID_ISAR2 = 2685337858
+    let UC_ARM_REG_ID_ISAR3 = 2685337859
+    let UC_ARM_REG_ID_ISAR4 = 2685337860
+    let UC_ARM_REG_ID_ISAR5 = 2685337861
+    let UC_ARM_REG_ID_ISAR6 = 2685337863
+    let UC_ARM_REG_ID_MMFR0 = 2685337732
+    let UC_ARM_REG_ID_MMFR1 = 2685337733
+    let UC_ARM_REG_ID_MMFR2 = 2685337734
+    let UC_ARM_REG_ID_MMFR3 = 2685337735
+    let UC_ARM_REG_ID_MMFR4 = 2685337862
+    let UC_ARM_REG_ID_PFR0 = 2685337728
+    let UC_ARM_REG_ID_PFR1 = 2685337729
+    let UC_ARM_REG_IFAR = 2685349890
+    let UC_ARM_REG_IFSR = 2685347841
+    let UC_ARM_REG_ISB = 2685352580
+    let UC_ARM_REG_ISR_EL1 = 2685362304
+    let UC_ARM_REG_ITLBIALL = 2685354624
+    let UC_ARM_REG_ITLBIASID = 2685354626
+    let UC_ARM_REG_ITLBIMVA = 2685354625
+    let UC_ARM_REG_JIDR = 2685272120
+    let UC_ARM_REG_JMCR = 2685276216
+    let UC_ARM_REG_JOSCR = 2685274168
+    let UC_ARM_REG_L2CTLR = 2685356042
+    let UC_ARM_REG_L2ECTLR = 2685356043
+    let UC_ARM_REG_MAIR0 = 2685358336
+    let UC_ARM_REG_MAIR1 = 2685358337
+    let UC_ARM_REG_MAIR_EL1 = 2417214736
+    let UC_ARM_REG_MAIR_EL3 = 2417227024
+    let UC_ARM_REG_MDCCINT_EL1 = 2685272320
+    let UC_ARM_REG_MDCCSR_EL0 = 2685272192
+    let UC_ARM_REG_MDRAR_EL1 = 2417197184
+    let UC_ARM_REG_MDSCR_EL1 = 2685272322
+    let UC_ARM_REG_MPIDR_EL1 = 2685337605
+    let UC_ARM_REG_MVA_prefetch = 2685353601
+    let UC_ARM_REG_NOP = 2685351940
+    let UC_ARM_REG_OSDLR_EL1 = 2685274500
+    let UC_ARM_REG_OSLAR_EL1 = 2685274116
+    let UC_ARM_REG_OSLSR_EL1 = 2685274244
+    let UC_ARM_REG_PAR = 2685352448
+    let UC_ARM_REG_PMCCFILTR = 2685368199
+    let UC_ARM_REG_PMCCFILTR_EL0 = 2417221503
+    let UC_ARM_REG_PMCCNTR = 2685357696
+    let UC_ARM_REG_PMCCNTR_EL0 = 2417220840
+    let UC_ARM_REG_PMCNTENCLR = 2685357570
+    let UC_ARM_REG_PMCNTENCLR_EL0 = 2417220834
+    let UC_ARM_REG_PMCNTENSET = 2685357569
+    let UC_ARM_REG_PMCNTENSET_EL0 = 2417220833
+    let UC_ARM_REG_PMCR = 2685357568
+    let UC_ARM_REG_PMCR_EL0 = 2417220832
+    let UC_ARM_REG_PMEVCNTR0 = 2685367296
+    let UC_ARM_REG_PMEVCNTR0_EL0 = 2417221440
+    let UC_ARM_REG_PMEVCNTR1 = 2685367297
+    let UC_ARM_REG_PMEVCNTR1_EL0 = 2417221441
+    let UC_ARM_REG_PMEVCNTR2 = 2685367298
+    let UC_ARM_REG_PMEVCNTR2_EL0 = 2417221442
+    let UC_ARM_REG_PMEVCNTR3 = 2685367299
+    let UC_ARM_REG_PMEVCNTR3_EL0 = 2417221443
+    let UC_ARM_REG_PMEVTYPER0 = 2685367808
+    let UC_ARM_REG_PMEVTYPER0_EL0 = 2417221472
+    let UC_ARM_REG_PMEVTYPER1 = 2685367809
+    let UC_ARM_REG_PMEVTYPER1_EL0 = 2417221473
+    let UC_ARM_REG_PMEVTYPER2 = 2685367810
+    let UC_ARM_REG_PMEVTYPER2_EL0 = 2417221474
+    let UC_ARM_REG_PMEVTYPER3 = 2685367811
+    let UC_ARM_REG_PMEVTYPER3_EL0 = 2417221475
+    let UC_ARM_REG_PMINTENCLR = 2685357826
+    let UC_ARM_REG_PMINTENCLR_EL1 = 2417214706
+    let UC_ARM_REG_PMINTENSET = 2685357825
+    let UC_ARM_REG_PMINTENSET_EL1 = 2417214705
+    let UC_ARM_REG_PMOVSCLR_EL0 = 2417220835
+    let UC_ARM_REG_PMOVSR = 2685357571
+    let UC_ARM_REG_PMOVSSET = 2685357827
+    let UC_ARM_REG_PMOVSSET_EL0 = 2417220851
+    let UC_ARM_REG_PMSELR = 2685357573
+    let UC_ARM_REG_PMSELR_EL0 = 2417220837
+    let UC_ARM_REG_PMSWINC = 2685357572
+    let UC_ARM_REG_PMSWINC_EL0 = 2417220836
+    let UC_ARM_REG_PMUSERENR = 2685357824
+    let UC_ARM_REG_PMUSERENR_EL0 = 2417220848
+    let UC_ARM_REG_PMXEVCNTR = 2685357698
+    let UC_ARM_REG_PMXEVCNTR_EL0 = 2417220842
+    let UC_ARM_REG_PMXEVTYPER = 2685357697
+    let UC_ARM_REG_PMXEVTYPER_EL0 = 2417220841
+    let UC_ARM_REG_SCTLR = 2685339648
+    let UC_ARM_REG_TCMTR = 2685337602
+    let UC_ARM_REG_TCR_EL1 = 2417213698
+    let UC_ARM_REG_TEECR = 2685272112
+    let UC_ARM_REG_TEEHBR = 2685274160
+    let UC_ARM_REG_TLBIALL = 2685354880
+    let UC_ARM_REG_TLBIALLIS = 2685354368
+    let UC_ARM_REG_TLBIASID = 2685354882
+    let UC_ARM_REG_TLBIASIDIS = 2685354370
+    let UC_ARM_REG_TLBIMVA = 2685354881
+    let UC_ARM_REG_TLBIMVAA = 2685354883
+    let UC_ARM_REG_TLBIMVAAIS = 2685354371
+    let UC_ARM_REG_TLBIMVAIS = 2685354369
+    let UC_ARM_REG_TLBTR = 2685337603
+    let UC_ARM_REG_TPIDRPRW = 2685364228
+    let UC_ARM_REG_TPIDRRO_EL0 = 2417221251
+    let UC_ARM_REG_TPIDRURO = 2685364227
+    let UC_ARM_REG_TPIDRURW = 2685364226
+    let UC_ARM_REG_TPIDR_EL0 = 2417221250
+    let UC_ARM_REG_TPIDR_EL1 = 2417215108
+    let UC_ARM_REG_TTBCR = 2685341698
+    let UC_ARM_REG_TTBR0 = 2685370624
+    let UC_ARM_REG_TTBR0_EL1 = 2685341696
+    let UC_ARM_REG_TTBR1 = 2685370632
+    let UC_ARM_REG_TTBR1_EL1 = 2685341697
+    let UC_ARM_REG_VBAR = 2685362176
+    let UC_ARM_REG_WFAR = 2685349889
+    let UC_ARM_REG_C1_C0_2 = 2685339650
+    let UC_ARM_REG_C13_C0_2 = 2685364226
+    let UC_ARM_REG_C13_C0_3 = 2685364227
+