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arm64: tegra: Add Tegra194 chip device tree
Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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‎arch/arm64/boot/dts/nvidia/tegra194.dtsi

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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/gpio/tegra194-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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/ {
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compatible = "nvidia,tegra194";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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/* control backbone */
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cbb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>;
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uarta: serial@3100000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03100000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTA>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTA>;
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reset-names = "serial";
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status = "disabled";
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};
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uartb: serial@3110000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03110000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTB>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTB>;
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reset-names = "serial";
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status = "disabled";
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};
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uartd: serial@3130000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03130000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTD>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTD>;
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reset-names = "serial";
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status = "disabled";
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};
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uarte: serial@3140000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03140000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTE>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTE>;
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reset-names = "serial";
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status = "disabled";
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};
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uartf: serial@3150000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03150000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTF>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTF>;
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reset-names = "serial";
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status = "disabled";
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};
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gen1_i2c: i2c@3160000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x03160000 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C1>;
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reset-names = "i2c";
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status = "disabled";
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};
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uarth: serial@3170000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03170000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTH>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTH>;
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reset-names = "serial";
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status = "disabled";
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};
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cam_i2c: i2c@3180000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x03180000 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C3>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux1 */
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dp_aux_ch1_i2c: i2c@3190000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x03190000 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C4>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux0 */
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dp_aux_ch0_i2c: i2c@31b0000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x031b0000 0x10000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C6>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C6>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen7_i2c: i2c@31c0000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x031c0000 0x10000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C7>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C7>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen9_i2c: i2c@31e0000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x031e0000 0x10000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C9>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C9>;
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reset-names = "i2c";
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status = "disabled";
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};
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sdmmc1: sdhci@3400000 {
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compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
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reg = <0x03400000 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA194_RESET_SDMMC1>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc3: sdhci@3440000 {
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compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
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reg = <0x03440000 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA194_RESET_SDMMC3>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc4: sdhci@3460000 {
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compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
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reg = <0x03460000 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA194_RESET_SDMMC4>;
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reset-names = "sdhci";
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status = "disabled";
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};
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gic: interrupt-controller@3881000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x03881000 0x1000>,
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<0x03882000 0x2000>,
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<0x03884000 0x2000>,
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<0x03886000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x03c00000 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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};
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gen2_i2c: i2c@c240000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x0c240000 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C2>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen8_i2c: i2c@c250000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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reg = <0x0c250000 0x10000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C8>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C8>;
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reset-names = "i2c";
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status = "disabled";
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};
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uartc: serial@c280000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x0c280000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTC>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTC>;
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reset-names = "serial";
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status = "disabled";
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};
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uartg: serial@c290000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x0c290000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTG>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTG>;
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reset-names = "serial";
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status = "disabled";
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};
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pmc@c360000 {
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compatible = "nvidia,tegra194-pmc";
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reg = <0x0c360000 0x10000>,
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<0x0c370000 0x10000>,
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<0x0c380000 0x10000>,
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<0x0c390000 0x10000>,
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<0x0c3a0000 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch", "misc";
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};
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};
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sysram@40000000 {
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compatible = "nvidia,tegra194-sysram", "mmio-sram";
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reg = <0x0 0x40000000 0x0 0x50000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40000000 0x50000>;
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cpu_bpmp_tx: shmem@4e000 {
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compatible = "nvidia,tegra194-bpmp-shmem";
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reg = <0x4e000 0x1000>;
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label = "cpu-bpmp-tx";
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pool;
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};
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cpu_bpmp_rx: shmem@4f000 {
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compatible = "nvidia,tegra194-bpmp-shmem";
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reg = <0x4f000 0x1000>;
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label = "cpu-bpmp-rx";
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pool;
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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bpmp_i2c: i2c {
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compatible = "nvidia,tegra186-bpmp-i2c";
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nvidia,bpmp-bus-id = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bpmp_thermal: thermal {
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compatible = "nvidia,tegra186-bpmp-thermal";
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#thermal-sensor-cells = <1>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&gic>;
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};
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};

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