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jysnpsFelipe Balbi
jysnps
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Felipe Balbi
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usb: dwc2: Remove platform static params
Remove the platform-specific static param structs and set only those params that are necessary for each platform. Signed-off-by: John Youn <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
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‎drivers/usb/dwc2/params.c

Lines changed: 108 additions & 154 deletions
Original file line numberDiff line numberDiff line change
@@ -38,166 +38,111 @@
3838

3939
#include "core.h"
4040

41-
static const struct dwc2_core_params params_hi6220 = {
42-
.otg_cap = 2, /* No HNP/SRP capable */
43-
.dma_desc_enable = 0,
44-
.dma_desc_fs_enable = 0,
45-
.speed = 0, /* High Speed */
46-
.enable_dynamic_fifo = 1,
47-
.en_multiple_tx_fifo = 1,
48-
.host_rx_fifo_size = 512,
49-
.host_nperio_tx_fifo_size = 512,
50-
.host_perio_tx_fifo_size = 512,
51-
.max_transfer_size = 65535,
52-
.max_packet_count = 511,
53-
.host_channels = 16,
54-
.phy_type = 1, /* UTMI */
55-
.phy_utmi_width = 8,
56-
.phy_ulpi_ddr = 0, /* Single */
57-
.phy_ulpi_ext_vbus = 0,
58-
.i2c_enable = 0,
59-
.ulpi_fs_ls = 0,
60-
.host_support_fs_ls_low_power = 0,
61-
.host_ls_low_power_phy_clk = 0, /* 48 MHz */
62-
.ts_dline = 0,
63-
.reload_ctl = 0,
64-
.ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
65-
GAHBCFG_HBSTLEN_SHIFT,
66-
.uframe_sched = 0,
67-
.external_id_pin_ctl = -1,
68-
.hibernation = -1,
69-
};
41+
static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
42+
{
43+
struct dwc2_core_params *p = &hsotg->params;
7044

71-
static const struct dwc2_core_params params_bcm2835 = {
72-
.otg_cap = 0, /* HNP/SRP capable */
73-
.dma_desc_enable = 0,
74-
.dma_desc_fs_enable = 0,
75-
.speed = 0, /* High Speed */
76-
.enable_dynamic_fifo = 1,
77-
.en_multiple_tx_fifo = 1,
78-
.host_rx_fifo_size = 774, /* 774 DWORDs */
79-
.host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
80-
.host_perio_tx_fifo_size = 512, /* 512 DWORDs */
81-
.max_transfer_size = 65535,
82-
.max_packet_count = 511,
83-
.host_channels = 8,
84-
.phy_type = 1, /* UTMI */
85-
.phy_utmi_width = 8, /* 8 bits */
86-
.phy_ulpi_ddr = 0, /* Single */
87-
.phy_ulpi_ext_vbus = 0,
88-
.i2c_enable = 0,
89-
.ulpi_fs_ls = 0,
90-
.host_support_fs_ls_low_power = 0,
91-
.host_ls_low_power_phy_clk = 0, /* 48 MHz */
92-
.ts_dline = 0,
93-
.reload_ctl = 0,
94-
.ahbcfg = 0x10,
95-
.uframe_sched = 0,
96-
.external_id_pin_ctl = -1,
97-
.hibernation = -1,
98-
};
45+
p->otg_cap = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
46+
p->speed = DWC2_SPEED_PARAM_HIGH;
47+
p->host_rx_fifo_size = 774;
48+
p->host_nperio_tx_fifo_size = 256;
49+
p->host_perio_tx_fifo_size = 512;
50+
p->max_transfer_size = 65535;
51+
p->max_packet_count = 511;
52+
p->host_channels = 8;
53+
p->phy_type = 1;
54+
p->phy_utmi_width = 8;
55+
p->i2c_enable = false;
56+
p->host_ls_low_power_phy_clk = 0;
57+
p->reload_ctl = false;
58+
p->ahbcfg = 0x10;
59+
p->uframe_sched = false;
60+
}
9961

100-
static const struct dwc2_core_params params_rk3066 = {
101-
.otg_cap = 2, /* non-HNP/non-SRP */
102-
.dma_desc_enable = 0,
103-
.dma_desc_fs_enable = 0,
104-
.speed = -1,
105-
.enable_dynamic_fifo = 1,
106-
.en_multiple_tx_fifo = -1,
107-
.host_rx_fifo_size = 525, /* 525 DWORDs */
108-
.host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
109-
.host_perio_tx_fifo_size = 256, /* 256 DWORDs */
110-
.max_transfer_size = -1,
111-
.max_packet_count = -1,
112-
.host_channels = -1,
113-
.phy_type = -1,
114-
.phy_utmi_width = -1,
115-
.phy_ulpi_ddr = -1,
116-
.phy_ulpi_ext_vbus = -1,
117-
.i2c_enable = -1,
118-
.ulpi_fs_ls = -1,
119-
.host_support_fs_ls_low_power = -1,
120-
.host_ls_low_power_phy_clk = -1,
121-
.ts_dline = -1,
122-
.reload_ctl = -1,
123-
.ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
124-
GAHBCFG_HBSTLEN_SHIFT,
125-
.uframe_sched = -1,
126-
.external_id_pin_ctl = -1,
127-
.hibernation = -1,
128-
};
62+
static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
63+
{
64+
struct dwc2_core_params *p = &hsotg->params;
12965

130-
static const struct dwc2_core_params params_ltq = {
131-
.otg_cap = 2, /* non-HNP/non-SRP */
132-
.dma_desc_enable = -1,
133-
.dma_desc_fs_enable = -1,
134-
.speed = -1,
135-
.enable_dynamic_fifo = -1,
136-
.en_multiple_tx_fifo = -1,
137-
.host_rx_fifo_size = 288, /* 288 DWORDs */
138-
.host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
139-
.host_perio_tx_fifo_size = 96, /* 96 DWORDs */
140-
.max_transfer_size = 65535,
141-
.max_packet_count = 511,
142-
.host_channels = -1,
143-
.phy_type = -1,
144-
.phy_utmi_width = -1,
145-
.phy_ulpi_ddr = -1,
146-
.phy_ulpi_ext_vbus = -1,
147-
.i2c_enable = -1,
148-
.ulpi_fs_ls = -1,
149-
.host_support_fs_ls_low_power = -1,
150-
.host_ls_low_power_phy_clk = -1,
151-
.ts_dline = -1,
152-
.reload_ctl = -1,
153-
.ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
154-
GAHBCFG_HBSTLEN_SHIFT,
155-
.uframe_sched = -1,
156-
.external_id_pin_ctl = -1,
157-
.hibernation = -1,
158-
};
66+
p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
67+
p->speed = DWC2_SPEED_PARAM_HIGH;
68+
p->host_rx_fifo_size = 512;
69+
p->host_nperio_tx_fifo_size = 512;
70+
p->host_perio_tx_fifo_size = 512;
71+
p->max_transfer_size = 65535;
72+
p->max_packet_count = 511;
73+
p->host_channels = 16;
74+
p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
75+
p->phy_utmi_width = 8;
76+
p->i2c_enable = false;
77+
p->host_ls_low_power_phy_clk = 0;
78+
p->reload_ctl = false;
79+
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
80+
GAHBCFG_HBSTLEN_SHIFT;
81+
p->uframe_sched = false;
82+
}
15983

160-
static const struct dwc2_core_params params_amlogic = {
161-
.otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
162-
.dma_desc_enable = 0,
163-
.dma_desc_fs_enable = 0,
164-
.speed = DWC2_SPEED_PARAM_HIGH,
165-
.enable_dynamic_fifo = 1,
166-
.en_multiple_tx_fifo = -1,
167-
.host_rx_fifo_size = 512,
168-
.host_nperio_tx_fifo_size = 500,
169-
.host_perio_tx_fifo_size = 500,
170-
.max_transfer_size = -1,
171-
.max_packet_count = -1,
172-
.host_channels = 16,
173-
.phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
174-
.phy_utmi_width = -1,
175-
.phy_ulpi_ddr = -1,
176-
.phy_ulpi_ext_vbus = -1,
177-
.i2c_enable = -1,
178-
.ulpi_fs_ls = -1,
179-
.host_support_fs_ls_low_power = -1,
180-
.host_ls_low_power_phy_clk = -1,
181-
.ts_dline = -1,
182-
.reload_ctl = 1,
183-
.ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
184-
GAHBCFG_HBSTLEN_SHIFT,
185-
.uframe_sched = 0,
186-
.external_id_pin_ctl = -1,
187-
.hibernation = -1,
188-
};
84+
static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
85+
{
86+
struct dwc2_core_params *p = &hsotg->params;
87+
88+
p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
89+
p->host_rx_fifo_size = 525;
90+
p->host_nperio_tx_fifo_size = 128;
91+
p->host_perio_tx_fifo_size = 256;
92+
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
93+
GAHBCFG_HBSTLEN_SHIFT;
94+
}
95+
96+
static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
97+
{
98+
struct dwc2_core_params *p = &hsotg->params;
99+
100+
p->otg_cap = 2;
101+
p->host_rx_fifo_size = 288;
102+
p->host_nperio_tx_fifo_size = 128;
103+
p->host_perio_tx_fifo_size = 96;
104+
p->max_transfer_size = 65535;
105+
p->max_packet_count = 511;
106+
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
107+
GAHBCFG_HBSTLEN_SHIFT;
108+
}
109+
110+
static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
111+
{
112+
struct dwc2_core_params *p = &hsotg->params;
113+
114+
p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
115+
p->speed = DWC2_SPEED_PARAM_HIGH;
116+
p->host_rx_fifo_size = 512;
117+
p->host_nperio_tx_fifo_size = 500;
118+
p->host_perio_tx_fifo_size = 500;
119+
p->host_channels = 16;
120+
p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
121+
p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
122+
GAHBCFG_HBSTLEN_SHIFT;
123+
p->uframe_sched = false;
124+
}
125+
126+
static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
127+
{
128+
struct dwc2_core_params *p = &hsotg->params;
129+
130+
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
131+
}
189132

190133
const struct of_device_id dwc2_of_match_table[] = {
191-
{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
192-
{ .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
193-
{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
194-
{ .compatible = "lantiq,arx100-usb", .data = &params_ltq },
195-
{ .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
196-
{ .compatible = "snps,dwc2", .data = NULL },
197-
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
198-
{ .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },
199-
{ .compatible = "amlogic,meson-gxbb-usb", .data = &params_amlogic },
200-
{ .compatible = "amcc,dwc-otg", .data = NULL },
134+
{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
135+
{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
136+
{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
137+
{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
138+
{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
139+
{ .compatible = "snps,dwc2" },
140+
{ .compatible = "samsung,s3c6400-hsotg" },
141+
{ .compatible = "amlogic,meson8b-usb",
142+
.data = dwc2_set_amlogic_params },
143+
{ .compatible = "amlogic,meson-gxbb-usb",
144+
.data = dwc2_set_amlogic_params },
145+
{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
201146
{},
202147
};
203148
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
@@ -771,9 +716,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
771716

772717
int dwc2_init_params(struct dwc2_hsotg *hsotg)
773718
{
719+
const struct of_device_id *match;
720+
void (*set_params)(void *data);
721+
774722
dwc2_set_default_params(hsotg);
775723
dwc2_get_device_properties(hsotg);
776724

725+
match = of_match_device(dwc2_of_match_table, hsotg->dev);
726+
if (match && match->data) {
727+
set_params = match->data;
728+
set_params(hsotg);
729+
}
730+
777731
dwc2_check_params(hsotg);
778732

779733
return 0;

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