soc: arm: st_stm32: Cleanup gpio function code.

All series STM32 have mostly the same GPIO architecture
and can share the same code for GPIO manipulation.
Functions of the external interrupt line control are also the same.
This patch extracts common code from them and put them into the 'common'
folder.

Functions of control GPIO of these series scattered in
soc/arm/st_stm32/stm32xx/ folders contain these functions:
stm32_gpio_flags_to_conf(), stm32_gpio_configure(), stm32_gpio_set(),
stm32_gpio_get, stm32_gpio_enable_int().
This patch merges them into the gpio_stm32.c file.

Signed-off-by: Song Qiang <[email protected]>

Author: cybertale

drivers/gpio/gpio_stm32.c

@@ -19,9 +19,17 @@
 #include "gpio_stm32.h"
 #include "gpio_utils.h"
 
+/* F1 series STM32 use AFIO register to configure interrupt generation
+ * and pinmux.
+ */
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+#include "afio_registers.h"
+#else
+#include "syscfg_registers.h"
+#endif
+
 /**
- * @brief Common GPIO driver for STM32 MCUs. Each SoC must implement a
- * SoC specific integration glue
+ * @brief Common GPIO driver for STM32 MCUs.
  */
 
 /**
@@ -37,6 +45,202 @@ static void gpio_stm32_isr(int line, void *arg)
 	}
 }
 
+/**
+ * @brief Common gpio flags to custom flags
+ */
+const int gpio_stm32_flags_to_conf(int flags, int *pincfg)
+{
+	int direction = flags & GPIO_DIR_MASK;
+	int pud = flags & GPIO_PUD_MASK;
+
+	if (pincfg == NULL) {
+		return -EINVAL;
+	}
+
+	if (direction == GPIO_DIR_OUT) {
+		*pincfg = STM32_PINCFG_MODE_OUTPUT;
+	} else {
+		/* pull-{up,down} maybe? */
+		*pincfg = STM32_PINCFG_MODE_INPUT;
+		if (pud == GPIO_PUD_PULL_UP) {
+			*pincfg |= STM32_PINCFG_PULL_UP;
+		} else if (pud == GPIO_PUD_PULL_DOWN) {
+			*pincfg |= STM32_PINCFG_PULL_DOWN;
+		} else {
+			/* floating */
+			*pincfg |= STM32_PINCFG_FLOATING;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Configure the hardware.
+ */
+int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
+{
+	volatile struct stm32_gpio *gpio =
+		(struct stm32_gpio *)(base_addr);
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+	int cnf, mode, mode_io;
+	int crpin = pin;
+
+	/* pins are configured in CRL (0-7) and CRH (8-15)
+	 * registers
+	 */
+	volatile u32_t *reg = &gpio->crl;
+
+	ARG_UNUSED(altf);
+
+	if (crpin > 7) {
+		reg = &gpio->crh;
+		crpin -= 8;
+	}
+
+	/* each port is configured by 2 registers:
+	 * CNFy[1:0]: Port x configuration bits
+	 * MODEy[1:0]: Port x mode bits
+	 *
+	 * memory layout is repeated for every port:
+	 *   |  CNF  |  MODE |
+	 *   | [0:1] | [0:1] |
+	 */
+
+	mode_io = (conf >> STM32_MODE_INOUT_SHIFT) & STM32_MODE_INOUT_MASK;
+
+	if (mode_io == STM32_MODE_INPUT) {
+		int in_pudpd = conf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
+
+		/* Pin configured in input mode */
+		/* Mode: 00 */
+		mode = mode_io;
+		/* Configuration values: */
+		/* 00: Analog mode */
+		/* 01: Floating input */
+		/* 10: Pull-up/Pull-Down */
+		cnf = (conf >> STM32_CNF_IN_SHIFT) & STM32_CNF_IN_MASK;
+
+		if (in_pudpd == STM32_PUPD_PULL_UP) {
+			/* enable pull up */
+			gpio->odr |= 1 << pin;
+		} else if (in_pudpd == STM32_PUPD_PULL_DOWN) {
+			/* or pull down */
+			gpio->odr &= ~(1 << pin);
+		}
+	} else {
+		/* Pin configured in output mode */
+		int mode_speed = ((conf >> STM32_MODE_OSPEED_SHIFT) &
+				   STM32_MODE_OSPEED_MASK);
+		/* Mode output possible values */
+		/* 01: Max speed 10MHz (default value) */
+		/* 10: Max speed 2MHz */
+		/* 11: Max speed 50MHz */
+		mode = mode_speed + mode_io;
+		/* Configuration possible values */
+		/* x0: Push-pull */
+		/* x1: Open-drain */
+		/* 0x: General Purpose Output */
+		/* 1x: Alternate Function Output */
+		cnf = ((conf >> STM32_CNF_OUT_0_SHIFT) & STM32_CNF_OUT_0_MASK) |
+		      (((conf >> STM32_CNF_OUT_1_SHIFT) & STM32_CNF_OUT_1_MASK)
+		       << 1);
+	}
+
+	/* clear bits */
+	*reg &= ~(0xf << (crpin * 4));
+	/* set bits */
+	*reg |= (cnf << (crpin * 4 + 2) | mode << (crpin * 4));
+#else
+	unsigned int mode, otype, ospeed, pupd;
+	unsigned int pin_shift = pin << 1;
+	unsigned int afr_bank = pin / 8;
+	unsigned int afr_shift = (pin % 8) << 2;
+	u32_t scratch;
+
+	mode = (conf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
+	otype = (conf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
+	ospeed = (conf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
+	pupd = (conf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
+
+	scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift);
+	gpio->moder = scratch | (mode << pin_shift);
+
+	scratch = gpio->ospeedr & ~(STM32_OSPEEDR_MASK << pin_shift);
+	gpio->ospeedr = scratch | (ospeed << pin_shift);
+
+	scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin);
+	gpio->otyper = scratch | (otype << pin);
+
+	scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
+	gpio->pupdr = scratch | (pupd << pin_shift);
+
+	scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
+	gpio->afr[afr_bank] = scratch | (altf << afr_shift);
+#endif
+	return 0;
+}
+
+/**
+ * @brief Enable EXTI of the specific line
+ */
+const int gpio_stm32_enable_int(int port, int pin)
+{
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+	volatile struct stm32_afio *syscfg =
+		(struct stm32_afio *)AFIO_BASE;
+#else
+	volatile struct stm32_syscfg *syscfg =
+		(struct stm32_syscfg *)SYSCFG_BASE;
+#endif
+	volatile union syscfg_exticr *exticr;
+
+#if defined(CONFIG_SOC_SERIES_STM32F2X) || \
+	defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32F4X) || \
+	defined(CONFIG_SOC_SERIES_STM32F7X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
+	struct stm32_pclken pclken = {
+		.bus = STM32_CLOCK_BUS_APB2,
+		.enr = LL_APB2_GRP1_PERIPH_SYSCFG
+	};
+	/* Enable SYSCFG clock */
+	clock_control_on(clk, (clock_control_subsys_t *) &pclken);
+#endif
+	int shift = 0;
+
+	if (pin <= 3) {
+		exticr = &syscfg->exticr1;
+	} else if (pin <= 7) {
+		exticr = &syscfg->exticr2;
+	} else if (pin <= 11) {
+		exticr = &syscfg->exticr3;
+	} else if (pin <= 15) {
+		exticr = &syscfg->exticr4;
+	} else {
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_SOC_SERIES_STM32L0X
+	/*
+	 * Ports F and G are not present on some STM32L0 parts, so
+	 * for these parts port H external interrupt should be enabled
+	 * by writing value 0x5 instead of 0x7.
+	 */
+	if (port == STM32_PORTH) {
+		port = LL_SYSCFG_EXTI_PORTH;
+	}
+#endif
+
+	shift = 4 * (pin % 4);
+
+	exticr->val &= ~(0xf << shift);
+	exticr->val |= port << shift;
+
+	return 0;
+}
+
 /**
  * @brief Configure pin or port
  */
@@ -54,12 +258,12 @@ static int gpio_stm32_config(struct device *dev, int access_op,
 	/* figure out if we can map the requested GPIO
 	 * configuration
 	 */
-	map_res = stm32_gpio_flags_to_conf(flags, &pincfg);
+	map_res = gpio_stm32_flags_to_conf(flags, &pincfg);
 	if (map_res) {
 		return map_res;
 	}
 
-	if (stm32_gpio_configure(cfg->base, pin, pincfg, 0)) {
+	if (gpio_stm32_configure(cfg->base, pin, pincfg, 0)) {
 		return -EIO;
 	}
 
@@ -70,7 +274,7 @@ static int gpio_stm32_config(struct device *dev, int access_op,
 			return -EBUSY;
 		}
 
-		stm32_gpio_enable_int(cfg->port, pin);
+		gpio_stm32_enable_int(cfg->port, pin);
 
 		if (flags & GPIO_INT_EDGE) {
 			int edge = 0;
@@ -100,12 +304,20 @@ static int gpio_stm32_write(struct device *dev, int access_op,
 			    u32_t pin, u32_t value)
 {
 	const struct gpio_stm32_config *cfg = dev->config->config_info;
+	struct stm32_gpio *gpio = (struct stm32_gpio *)cfg->base;
+	int pval = 1 << (pin & 0xf);
 
 	if (access_op != GPIO_ACCESS_BY_PIN) {
 		return -ENOTSUP;
 	}
 
-	return stm32_gpio_set(cfg->base, pin, value);
+	if (value != 0) {
+		gpio->odr |= pval;
+	} else {
+		gpio->odr &= ~pval;
+	}
+
+	return 0;
 }
 
 /**
@@ -115,12 +327,13 @@ static int gpio_stm32_read(struct device *dev, int access_op,
 			   u32_t pin, u32_t *value)
 {
 	const struct gpio_stm32_config *cfg = dev->config->config_info;
+	struct stm32_gpio *gpio = (struct stm32_gpio *)cfg->base;
 
 	if (access_op != GPIO_ACCESS_BY_PIN) {
 		return -ENOTSUP;
 	}
 
-	*value = stm32_gpio_get(cfg->base, pin);
+	*value = (gpio->idr >> pin) & 0x1;
 
 	return 0;
 }

drivers/gpio/gpio_stm32.h

@@ -104,6 +104,20 @@
 #define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI
 #endif /* CONFIG_SOC_SERIES_.. */
 
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+#define STM32_PINCFG_MODE_OUTPUT	STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT | STM32_CNF_PUSH_PULL
+#define STM32_PINCFG_MODE_INPUT		STM32_MODE_INPUT
+#define STM32_PINCFG_PULL_UP		STM32_CNF_IN_PUPD | STM32_PUPD_PULL_UP
+#define STM32_PINCFG_PULL_DOWN		STM32_CNF_IN_PUPD | STM32_PUPD_PULL_DOWN
+#define STM32_PINCFG_FLOATING		STM32_CNF_IN_FLOAT | STM32_PUPD_NO_PULL
+#else
+#define STM32_PINCFG_MODE_OUTPUT	STM32_MODER_OUTPUT_MODE
+#define STM32_PINCFG_MODE_INPUT		STM32_MODER_INPUT_MODE
+#define STM32_PINCFG_PULL_UP		STM32_PUPDR_PULL_UP
+#define STM32_PINCFG_PULL_DOWN		STM32_PUPDR_PULL_DOWN
+#define STM32_PINCFG_FLOATING		STM32_PUPDR_NO_PULL
+#endif /* CONFIG_SOC_SERIES_STM32F1X */
+
 /**
  * @brief configuration of GPIO device
  */
@@ -126,14 +140,39 @@ struct gpio_stm32_data {
 };
 
 /**
- * @brief helper for mapping of GPIO flags to SoC specific config
- *
- * @param flags GPIO encoded flags
- * @param out conf SoC specific pin config
- *
- * @return 0 if flags were mapped to SoC pin config
+ * @brief layout of stm32 gpio registers
  */
-int stm32_gpio_flags_to_conf(int flags, int *conf);
+struct stm32_gpio {
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+	u32_t crl;
+	u32_t crh;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t brr;
+	u32_t lckr;
+#else
+	u32_t moder;
+	u32_t otyper;
+	u32_t ospeedr;
+	u32_t pupdr;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t lckr;
+	u32_t afr[2];
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32F7X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	u32_t brr;
+#endif
+#ifdef CONFIG_SOC_SERIES_STM32L4X
+	u32_t ascr;
+#endif
+#endif /* CONFIG_SOC_SERIES_STM32F1X */
+};
 
 /**
  * @brief helper for configuration of GPIO pin
@@ -143,32 +182,6 @@ int stm32_gpio_flags_to_conf(int flags, int *conf);
  * @param func GPIO mode
  * @param altf Alternate function
  */
-int stm32_gpio_configure(u32_t *base_addr, int pin, int func, int altf);
-
-/**
- * @brief helper for setting of GPIO pin output
- *
- * @param base_addr GPIO port base address
- * @param pin IO pin
- * @param value 1, 0
- */
-int stm32_gpio_set(u32_t *base, int pin, int value);
-
-/**
- * @brief helper for reading of GPIO pin value
- *
- * @param base_addr GPIO port base address
- * @param pin IO pin
- * @return pin value
- */
-int stm32_gpio_get(u32_t *base, int pin);
-
-/**
- * @brief enable interrupt source for GPIO pin
- * @param port
- * @param pin
- */
-int stm32_gpio_enable_int(int port, int pin);
+int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf);
 
 #endif /* ZEPHYR_DRIVERS_GPIO_GPIO_STM32_H_ */
-

drivers/pinmux/stm32/pinmux_stm32.c

@@ -105,7 +105,7 @@ static int stm32_pin_configure(int pin, int func, int altf)
 	/* not much here, on STM32F10x the alternate function is
 	 * controller by setting up GPIO pins in specific mode.
 	 */
-	return stm32_gpio_configure((u32_t *)port_base,
+	return gpio_stm32_configure((u32_t *)port_base,
 				    STM32_PIN(pin), func, altf);
 }