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ext: hal: atmel: sam: re-add missing header symbols following HAL import
Following the HAL import, reapply the part of commit 1333061 ("Add missing header files symbols for Atmel SAM E70") which hasn't been fixed upstream yet. From this commit, only the DACC alternate pin functions have been fixed. Signed-off-by: Aurelien Jarno <[email protected]>
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‎ext/hal/atmel/asf/sam/include/same70/README

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@@ -34,3 +34,9 @@ License:
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License Link:
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https://www.apache.org/licenses/LICENSE-2.0
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Patch Lst:
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* Add missing header files symbols for Atmel SAM E70
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Several missing symbols for same70q21 SoC are added:
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- TC Channel Mode Register: Waveform Mode definitions
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- Legacy peripheral IDs definitions

‎ext/hal/atmel/asf/sam/include/same70/component/tc.h

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@@ -190,6 +190,86 @@ typedef union {
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#define TC_CMR_SBSMPLR_FOURTH (TC_CMR_SBSMPLR_FOURTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */
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#define TC_CMR_SBSMPLR_EIGHTH (TC_CMR_SBSMPLR_EIGHTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */
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#define TC_CMR_SBSMPLR_SIXTEENTH (TC_CMR_SBSMPLR_SIXTEENTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */
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#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
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#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
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#define TC_CMR_EEVTEDG_Pos 8
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#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
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#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))
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#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
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#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
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#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
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#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
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#define TC_CMR_EEVT_Pos 10
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#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
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#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))
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#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
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#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
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#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
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#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
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#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
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#define TC_CMR_WAVSEL_Pos 13
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#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
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#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))
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#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
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#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
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#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
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#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
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#define TC_CMR_ACPA_Pos 16
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#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
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#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))
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#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
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#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
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#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_ACPC_Pos 18
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#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
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#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))
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#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
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#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
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#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_AEEVT_Pos 20
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#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
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#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))
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#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
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#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
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#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_ASWTRG_Pos 22
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#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
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#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))
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#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
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#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
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#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_BCPB_Pos 24
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#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
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#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))
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#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
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#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
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#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_BCPC_Pos 26
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#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
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#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))
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#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
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#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
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#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_BEEVT_Pos 28
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#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
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#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))
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#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
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#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
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#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_BSWTRG_Pos 30
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#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
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#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))
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#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
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#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
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#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
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#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
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#define TC_CMR_MASK _U_(0x7FC7FF) /**< \deprecated (TC_CMR) Register MASK (Use TC_CMR_Msk instead) */
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#define TC_CMR_Msk _U_(0x7FC7FF) /**< (TC_CMR) Register Mask */
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‎ext/hal/atmel/asf/sam/include/same70/same70q21.h

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@@ -593,18 +593,18 @@ void XDMAC_Handler ( void );
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/* ************************************************************************** */
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/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */
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/* ************************************************************************** */
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#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0
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#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1
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#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2
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#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0
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#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1
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#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2
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#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0
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#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1
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#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2
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#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0
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#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1
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#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2
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#define ID_TC0 ID_TC0_CHANNEL0
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#define ID_TC1 ID_TC0_CHANNEL1
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#define ID_TC2 ID_TC0_CHANNEL2
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#define ID_TC3 ID_TC1_CHANNEL0
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#define ID_TC4 ID_TC1_CHANNEL1
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#define ID_TC5 ID_TC1_CHANNEL2
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#define ID_TC6 ID_TC2_CHANNEL0
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#define ID_TC7 ID_TC2_CHANNEL1
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#define ID_TC8 ID_TC2_CHANNEL2
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#define ID_TC9 ID_TC3_CHANNEL0
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#define ID_TC10 ID_TC3_CHANNEL1
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#define ID_TC11 ID_TC3_CHANNEL2
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/** @} end of Legacy Peripheral Ids Definitions */
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/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions

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