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/* SoC level DTS fixup file */
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/* CCM configuration */
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- #define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
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- #define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
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+ #define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
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+ #define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
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- #define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_0_BASE_ADDRESS
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- #define DT_ICCM_SIZE (DT_ARC_ICCM_0_SIZE >> 10)
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+ #define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_0_BASE_ADDRESS
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+ #define DT_ICCM_SIZE (DT_ARC_ICCM_0_SIZE >> 10)
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+
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+ #define DT_DDR_BASE_ADDRESS DT_MMIO_SRAM_10000000_BASE_ADDRESS
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+ #define DT_DDR_SIZE (DT_MMIO_SRAM_10000000_SIZE >> 10)
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/*
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* UART configuration
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* DRAM includes the exception vector table at reset, which is at
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* the beginning of the region.
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*/
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- #if defined(DT_MMIO_SRAM_0_BASE_ADDRESS ) && (DT_MMIO_SRAM_0_SIZE > 0)
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- #define SRAM_START DT_MMIO_SRAM_0_BASE_ADDRESS
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- #define SRAM_SIZE (DT_MMIO_SRAM_0_SIZE >> 10)
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+ #if defined(DT_DDR_BASE_ADDRESS ) && (DT_DDR_SIZE > 0)
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+ #define SRAM_START DT_DDR_BASE_ADDRESS
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+ #define SRAM_SIZE DT_DDR_SIZE
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#endif
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/* Instruction Closely Coupled Memory (ICCM) base address and size */
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