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Revert "liverpool: Implement PM4 MEM_SEMAPHORE. (shadps4-emu#2235)"
This reverts commit a5a1253. Revert "shader_recompiler: Fix image write swizzles. (shadps4-emu#2236)" This reverts commit a51c8c1.
1 parent 029e6d2 commit f481e66

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4 files changed

+6
-114
lines changed

4 files changed

+6
-114
lines changed

src/shader_recompiler/ir/passes/resource_tracking_pass.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -569,7 +569,7 @@ void PatchTextureBufferArgs(IR::Block& block, IR::Inst& inst, Info& info) {
569569
inst.SetArg(1, CalculateBufferAddress(ir, inst, info, buffer, 1U));
570570

571571
if (inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32) {
572-
const auto swizzled = ApplySwizzle(ir, inst.Arg(2), buffer.DstSelect().Inverse());
572+
const auto swizzled = ApplySwizzle(ir, inst.Arg(2), buffer.DstSelect());
573573
const auto converted =
574574
ApplyWriteNumberConversionVec4(ir, swizzled, buffer.GetNumberConversion());
575575
inst.SetArg(2, converted);
@@ -829,7 +829,7 @@ void PatchImageArgs(IR::Block& block, IR::Inst& inst, Info& info) {
829829
auto texel = inst.Arg(4);
830830
if (is_storage) {
831831
// Storage image requires shader swizzle.
832-
texel = ApplySwizzle(ir, texel, image.DstSelect().Inverse());
832+
texel = ApplySwizzle(ir, texel, image.DstSelect());
833833
}
834834
const auto converted =
835835
ApplyWriteNumberConversionVec4(ir, texel, image.GetNumberConversion());

src/video_core/amdgpu/liverpool.cpp

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -641,18 +641,6 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
641641
}
642642
break;
643643
}
644-
case PM4ItOpcode::MemSemaphore: {
645-
const auto* mem_semaphore = reinterpret_cast<const PM4CmdMemSemaphore*>(header);
646-
if (mem_semaphore->IsSignaling()) {
647-
mem_semaphore->Signal();
648-
} else {
649-
while (!mem_semaphore->Signaled()) {
650-
YIELD_GFX();
651-
}
652-
mem_semaphore->Decrement();
653-
}
654-
break;
655-
}
656644
case PM4ItOpcode::AcquireMem: {
657645
// const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header);
658646
break;
@@ -891,18 +879,6 @@ Liverpool::Task Liverpool::ProcessCompute(const u32* acb, u32 acb_dwords, u32 vq
891879
}
892880
break;
893881
}
894-
case PM4ItOpcode::MemSemaphore: {
895-
const auto* mem_semaphore = reinterpret_cast<const PM4CmdMemSemaphore*>(header);
896-
if (mem_semaphore->IsSignaling()) {
897-
mem_semaphore->Signal();
898-
} else {
899-
while (!mem_semaphore->Signaled()) {
900-
YIELD_ASC(vqid);
901-
}
902-
mem_semaphore->Decrement();
903-
}
904-
break;
905-
}
906882
case PM4ItOpcode::WaitRegMem: {
907883
const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
908884
ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);

src/video_core/amdgpu/pm4_cmds.h

Lines changed: 0 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -886,65 +886,4 @@ struct PM4CmdDrawIndexIndirectMulti {
886886
u32 draw_initiator; ///< Draw Initiator Register
887887
};
888888

889-
struct PM4CmdMemSemaphore {
890-
enum class ClientCode : u32 {
891-
CommandProcessor = 0u,
892-
CommandBuffer = 1u,
893-
DataBuffer = 2u,
894-
};
895-
enum class Select : u32 {
896-
SignalSemaphore = 6u,
897-
WaitSemaphore = 7u,
898-
};
899-
enum class SignalType : u32 {
900-
Increment = 0u,
901-
Write = 1u,
902-
};
903-
904-
PM4Type3Header header; ///< header
905-
union {
906-
u32 dw1;
907-
BitField<3, 29, u32> addr_lo; ///< Semaphore address bits [31:3]
908-
};
909-
union {
910-
u32 dw2;
911-
BitField<0, 8, u32> addr_hi; ///< Semaphore address bits [39:32]
912-
BitField<16, 1, u32> use_mailbox; ///< Enables waiting until mailbox is written to
913-
BitField<20, 1, SignalType> signal_type; ///< Indicates the type of signal sent
914-
BitField<24, 2, ClientCode> client_code;
915-
BitField<29, 3, Select> sem_sel; ///< Indicates whether to do a signal or wait operation
916-
};
917-
918-
template <typename T>
919-
[[nodiscard]] T Address() const {
920-
return std::bit_cast<T>(u64(addr_lo) << 3 | (u64(addr_hi) << 32));
921-
}
922-
923-
[[nodiscard]] bool IsSignaling() const {
924-
return sem_sel == Select::SignalSemaphore;
925-
}
926-
927-
[[nodiscard]] bool Signaled() const {
928-
return *Address<u64*>() > 0;
929-
}
930-
931-
void Decrement() const {
932-
*Address<u64*>() -= 1;
933-
}
934-
935-
void Signal() const {
936-
auto* ptr = Address<u64*>();
937-
switch (signal_type) {
938-
case SignalType::Increment:
939-
*ptr += 1;
940-
break;
941-
case SignalType::Write:
942-
*ptr = 1;
943-
break;
944-
default:
945-
UNREACHABLE_MSG("Unknown signal type {}", static_cast<u32>(signal_type.Value()));
946-
}
947-
}
948-
};
949-
950889
} // namespace AmdGpu

src/video_core/amdgpu/types.h

Lines changed: 4 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -200,10 +200,10 @@ enum class NumberConversion : u32 {
200200
};
201201

202202
struct CompMapping {
203-
CompSwizzle r;
204-
CompSwizzle g;
205-
CompSwizzle b;
206-
CompSwizzle a;
203+
CompSwizzle r : 3;
204+
CompSwizzle g : 3;
205+
CompSwizzle b : 3;
206+
CompSwizzle a : 3;
207207

208208
auto operator<=>(const CompMapping& other) const = default;
209209

@@ -217,15 +217,6 @@ struct CompMapping {
217217
};
218218
}
219219

220-
[[nodiscard]] CompMapping Inverse() const {
221-
CompMapping result{};
222-
InverseSingle(result.r, CompSwizzle::Red);
223-
InverseSingle(result.g, CompSwizzle::Green);
224-
InverseSingle(result.b, CompSwizzle::Blue);
225-
InverseSingle(result.a, CompSwizzle::Alpha);
226-
return result;
227-
}
228-
229220
private:
230221
template <typename T>
231222
T ApplySingle(const std::array<T, 4>& data, const CompSwizzle swizzle) const {
@@ -246,20 +237,6 @@ struct CompMapping {
246237
UNREACHABLE();
247238
}
248239
}
249-
250-
void InverseSingle(CompSwizzle& dst, const CompSwizzle target) const {
251-
if (r == target) {
252-
dst = CompSwizzle::Red;
253-
} else if (g == target) {
254-
dst = CompSwizzle::Green;
255-
} else if (b == target) {
256-
dst = CompSwizzle::Blue;
257-
} else if (a == target) {
258-
dst = CompSwizzle::Alpha;
259-
} else {
260-
dst = CompSwizzle::Zero;
261-
}
262-
}
263240
};
264241

265242
inline DataFormat RemapDataFormat(const DataFormat format) {

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