Windows 11 with both KiCAD5/6/7/8 generate_netlist and generate_svg fail

[GinGawnKwong]

Discussed in #234

^{Originally posted by GinGawnKwong December 11, 2024}

here is a demo code from the document 
from skidl import *

# Create part templates.
q = Part("Device", "Q_PNP_CBE", dest=TEMPLATE)
r = Part("Device", "R", dest=TEMPLATE)

# Create nets.
gnd, vcc = Net("GND"), Net("VCC")
a, b, a_and_b = Net("A"), Net("B"), Net("A_AND_B")

# Instantiate parts.
gndt = Part("power", "GND")             # Ground terminal.
vcct = Part("power", "VCC")             # Power terminal.
q1, q2 = q(2)                           # Two transistors.
r1, r2, r3, r4, r5 = r(5, value="10K")  # Five 10K resistors.

# Make connections between parts.
a & r1 & q1["B C"] & r4 & q2["B C"] & a_and_b & r5 & gnd
b & r2 & q1["B"]
q1["C"] & r3 & gnd
vcc += q1["E"], q2["E"], vcct
gnd += gndt

# generate_schematic()
generate_netlist(tool=KICAD6)   # Create KICAD version 6 netlist.
# Create KICAD version 8 netlist.

In this demo,it show up with error :ERROR: No footprint for GND/#PWR1. @ [f:\GDUT\EDA\skidl-master\mytest\mytest_1.py:25]

I had set the KICAD6/7/8's symbol_dir right, but in the nest demo it just ran succeeded.but the generate_svg still fail

from skidl import *

# Create input & output voltages and ground reference.
vin, vout, gnd = Net('VI'), Net('VO'), Net('GND')

# Create two resistors.
r1, r2 = 2 * Part("Device", 'R', TEMPLATE, footprint='Resistor_SMD.pretty:R_0805_2012Metric')
r1.value = '1K'   # Set upper resistor value.
r2.value = '500'  # Set lower resistor value.

# Connect the nets and resistors.
vin += r1[1]      # Connect the input to the upper resistor.
gnd += r2[2]      # Connect the lower resistor to ground.
vout += r1[2], r2[1] # Output comes from the connection of the two resistors.

# Or you could do it with a single line of code:
# vin && r1 && vout && r2 && gnd

# Output the netlist to a file.
generate_netlist(tool=KICAD6)
generate_svg()
# generate_schematic()
```</div>

[devbisme]

I've found an error in SKiDL where generating a netlist, schematic, SVG, etc. corrupts the stored data so that creating anything after that runs into a problem. I have a fix for that and will release SKiDL 2.0.1 soon.

Also, generate_schematic only works with KICAD5. More modern versions of KiCad aren't supported.

[devbisme]

Fixed in release 2.0.1.

[cyberhuman]

After updating to 2.0.1, I noticed my existing code doesn't produce many netlist names anymore.
The minimal reproducer is:

RR = Part('Device', 'R', value='1k')
SW = Part('Switch', 'SW_DPST')

#SW[1] & SW[2]
SW[3] & SW[4]

gnd = Net('GND')

RR[1] & SW[1, 3] & gnd
RR[2] & gnd

generate_netlist()

In the netlist, the GND net is named N$1 instead of GND. Any clue what's causing this?
This particular circuit isn't exactly correct, but the net names should still be correct?
I will try to find another reproducer with a better circuit since other networks not connected to SW are also affected.

[devbisme]

I'll look into this.

[cyberhuman]

It looks like it's order-dependent. If a named net is added later than automatic net was created, the name is not propagated properly.

RR = Part('Device', 'R', dest=TEMPLATE)
RR1 = RR(value='1M')
RR2 = RR(value='2M')
RR3 = RR(value='3M')

(RR1 & RR2) | RR3 # results in `N$2` and `N$3`
RR1[1] += Net('net1')
RR2[2] += Net('net2')
#(RR1 & RR2) | RR3 # results in `net1` and `net2`

generate_netlist()

[devbisme]

I have a fix for this in the development branch. Give it a try and see if it works for you.

[cyberhuman]

Tested and works great! Thank you!