Adding push2/pop2 #116035
Adding push2/pop2 #116035
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@dotnet/samsung Could you please take a look? These changes may be related to riscv64. |
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Pull Request Overview
This PR introduces support for the new PUSH2/POP2 instructions and PPX features, updating the unwind, instruction, and code generation infrastructure accordingly.
- Adds new unwind functions (unwindPush2, unwindPush2Pop2CFI, etc.) and APX PPX handling for various architectures.
- Updates configuration, instruction definitions, emitter logic, and unit tests to integrate the new instructions.
Reviewed Changes
Copilot reviewed 17 out of 17 changed files in this pull request and generated 1 comment.
Show a summary per file
| File | Description |
|---|---|
| src/coreclr/jit/unwindx86.cpp | Added an empty unwindPush2() function; may need implementation to simulate push2. |
| src/coreclr/jit/unwindriscv64.cpp | Added unwindPush2() with an unreached() call as a placeholder for RISCV64. |
| src/coreclr/jit/unwindloongarch64.cpp | Added unwindPush2() with unreached() for LoongArch64. |
| src/coreclr/jit/unwindarm64.cpp | Added unwindPush2() with unreached() for ARM64. |
| src/coreclr/jit/unwindamd64.cpp | Implements unwindPush2() for AMD64, including a Windows-specific path using two pushes. |
| src/coreclr/jit/unwind.cpp | Added unwindPush2Pop2CFI() as a placeholder for CFI unwind handling for push2/pop2. |
| src/coreclr/jit/jitconfigvalues.h | Introduces the EnableApxPPX configuration integer. |
| src/coreclr/jit/instrsxarch.h | Defines push2 and pop2 instructions with APX-related flags. |
| src/coreclr/jit/instr.h | Adds new insOpts related to APX PPX hint. |
| src/coreclr/jit/instr.cpp | Updates instruction display and generation routines to handle new APX/PPX context. |
| src/coreclr/jit/emitxarch.h & .cpp | Adds helper functions for setting APX PPX context during instruction emission. |
| src/coreclr/jit/emit.h & .cpp | Adds new member functions and the HasApxPpx() helper for APX PPX functionality. |
| src/coreclr/jit/compiler.h | Declares new unwindPush2 and unwindPush2Windows functions. |
| src/coreclr/jit/codegenxarch.cpp | Integrates push2/pop2 emission for unit tests and updates prolog/epilog register handling. |
| src/coreclr/jit/codegen.h | Declares the instGen_Push2Pop2Ppx function and APX-specific pop routines. |
src/coreclr/jit/unwindx86.cpp
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| @@ -50,6 +50,10 @@ void Compiler::unwindPush(regNumber reg) | |||
| { | |||
| } | |||
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| void Compiler::unwindPush2(regNumber reg1, regNumber reg2) | |||
| { | |||
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The implementation of unwindPush2 in unwindx86.cpp is empty; consider simulating push2 by calling unwindPush() for each register to match the intent stated in the PR description.
| { | |
| { | |
| unwindPush(reg1); | |
| unwindPush(reg2); |
Copilot uses AI. Check for mistakes.
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@kunalspathak @EgorBo This PR is ready for review |
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| { | ||
| switch (ins) | ||
| { | ||
| case INS_push: |
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can you explain why INS_push and INS_pop is also in this? I was expecting just push2/pop2?
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INS_push and INS_pop has a PPX feature that's part of APX
PPX (push-pop acceleration) : A PPX hint that helps processor tracks these new instructions internally and fast-forwards register data between matching PUSH2 and POP2 instructions without going through memory. This is also applicable for PUSH/POP with REX2 encoding
| @@ -3782,6 +3782,20 @@ const IS_INFO emitter::emitGetSchedInfo(insFormat insFmt) | |||
| assert(!"Unsupported insFmt"); | |||
| return IS_NONE; | |||
| } | |||
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| bool emitter::HasApxPpx(instruction ins) | |||
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can you add summary docs explaining what is the scenario in which this method is used and what inference we can make from it?
src/coreclr/jit/unwindarm64.cpp
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| @@ -230,6 +230,11 @@ void Compiler::unwindPush(regNumber reg) | |||
| unreached(); // use one of the unwindSaveReg* functions instead. | |||
| } | |||
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| void Compiler::unwindPush2(regNumber reg1, regNumber reg2) | |||
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instead of touching other platform files, can you just add unwindPush2 for TARGET_AMD64 itself?
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Made the change
src/coreclr/jit/codegenxarch.cpp
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| // This is not a funclet or an On-Stack Replacement. | ||
| assert((compiler->funCurrentFunc()->funKind == FuncKind::FUNC_ROOT) && !compiler->opts.IsOSR()); | ||
| // PUSH2 doesn't work for ESP. | ||
| assert((rsPushRegs & RBM_SPBASE) == 0); |
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any reason why this code is not in its own method genPushCalleeSavedRegistersFromMaskAPX similar to genPopCalleeSavedRegistersFromMaskAPX?
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Created a genPushCalleeSavedRegistersFromMaskAPX and moved code there
| } | ||
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| int index = 0; | ||
| if (regStack.Height() % 2 == 1) |
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I think the answer is NO, but just want to double check -
does it matter (mainly perfwise) if you should use push2/pop2 for same set of registers or is it ok to use different pattern?
push2 rax, rbx
push rcx
...
..
pop2 rcx, rbx
pop raxinstead of
push2 rax, rbx
push rcx
...
..
pop rcx
pop rbx, raxThere was a problem hiding this comment.
In this case, it does matter
- The data being pushed/popped by PUSH2/POP2 must be 16B-aligned on the stack. This is why I'm always emitting a single
pushbefore any 'push2' and a singlepopbefore function end and after anypop2'.alignReg` is used to determine which register is used for this - I'm using the PPX feature whenever I'm using
push2/pop2. This is because the current guidance is to use push2/pop2 only with PPX
A PUSH and its corresponding POP may be marked with a 1-bit
Push-Pop Acceleration (PPX) hint to indicate that the POP reads the value written by the PUSH from the
stack. The processor tracks these marked instructions internally and fast-forwards register data between
matching PUSH and POP instructions, without going through memory or through the training loop of the
Fast Store Forwarding Predictor (FSFP).
When applying the PPX hint, the compiler needs to make sure that it always marks both the PUSH and its
matching POP (i.e., the POP which reads from the same stack memory address that the PUSH writes to).
This balancing rule naturally applies to PUSH/POP sequences in function prologs/epilogs, respectively. It
does not apply to standalone PUSH sequences, such as function argument pushes onto the stack. Such
sequences should not be marked with the PPX hint
src/coreclr/jit/emitxarch.h
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| } | ||
| else | ||
| { | ||
| assert((instOptions & INS_OPTS_APX_ppx_MASK) == 0); |
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this is always true because it is inside else of the opposite condition.
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Removed else
| @@ -20309,6 +20341,15 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins | |||
| } | |||
| break; | |||
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| case INS_push2: | |||
| // TODO-XArch-APX: to be verified. | |||
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I checked internally and this is the guidance I received. https://uops.info/table.html doesn't have these new instructions yet. That's why I marked it as a ToDo
| // id - instruction descriptor | ||
| // instOptions - emit options | ||
| // | ||
| void SetApxPpxIfNeeded(instrDesc* id, insOpts instOptions) |
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assert(HasApxPpx(id->idIns())) asserts id it's not any of the 4 instructions. Did you mean a difference check?
| // Setting EVEX.W = 1 bit indicates a push-pop acceleration (PPX) hint | ||
| // The current recommendation is to use PUSH2/POP2 only with PPX hint | ||
| // So, it is used only in Epilog/Prolog code generation | ||
| if (id->idIsApxPpxContextSet()) |
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isn't it always true for push2 and pop2?
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push2/pop2 are new instructions. PPX is a feature which push'/pop/pop2/push2can use. So theoretically, we might have apush2/pop2withoutPPX enabled. We currently only use push2/pop2 with PPX since that's the guidance(the guidance is for performance reasons) but that doesn't mean push2/pop2 cannot be used without PPX
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Added some comments.
Superpmi result with/without PPX feature
Did you get a chance to check if all the perfscore is coming just from prolog and epilog? Also, is it because we have not setup the perf latency/throughput numbers accurately (I see a TODO there and added a comment about it) and hence perfscore is just because of reduced in number of instructions?
I did check and it's entirely coming from The guidance I got was |
PR Overview
This PR does the following
APX and PPX
As part of Intel APX(Intel Advanced Performance Extensions), a couple of new features are available for working with stack
This write up with be focused on push2/pop2.
PUSH2/POP2
PUSH2 and POP2 are two new instructions for (respectively) pushing/popping 2 GPRs at a time to/from
the stack. These instructions use eEVEX encoding. The data being pushed/popped by PUSH2/POP2 must be 16B-aligned on the stack.
Guidance from Intel
It’s not part of the spec but in current implementations, push2/pop2 should really only be used with PPX hints and thus should only be used in matching “pairs”. i.e.
Unwind code
Windows does not current support unwind for push2. After discussion with Kunal, I decided to use 2
unwwind_push()to simulatepush2. This will need to be updated later once we have supportTesting done
Superpmi result with/without PPX feature
Diffs are based on 2,602,472 contexts (1,012,864 MinOpts, 1,589,608 FullOpts).
MISSED contexts: 17 (0.00%)
Base JIT options: JitBypassApxCheck=1
Diff JIT options: EnableApxPPX=1;JitBypassApxCheck=1
Overall (+15,581,843 bytes)
MinOpts (+527,206 bytes)
FullOpts (+15,054,637 bytes)
Sample diff
-6 (-17.65%) : 17249.dasm - System.Globalization.CalendarData:LoadCalendarDataFromSystemCore(System.String,ushort):bool:this (FullOpts)
-6 (-16.67%) : 7885.dasm - Microsoft.Extensions.Logging.LoggerMessage+<>c__DisplayClass12_0`2[int,System.__Canon]:b__1(Microsoft.Extensions.Logging.ILogger,int,System.__Canon,System.Exception):this (FullOpts)
-9 (-16.67%) : 13852.dasm - System.Linq.Enumerable+ArrayWhereSelectIterator`2[System.__Canon,System.__Canon]:GetCount(bool,System.ReadOnlySpan`1[System.__Canon],System.Func`2[System.__Canon,bool],System.Func`2[System.__Canon,System.__Canon]):int (FullOpts)