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Arm64 SVE: Add AndNot/OrNot APIs #116628

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@a74nh a74nh commented Jun 13, 2025

Fixes: #115244

The API review (#93887) approved OrNot as being both NOR and ORN. It can only match to one API, specifically NOR.
ORN could be matched in the future by optimising: Sve.Or(a, Sve.Not(b))

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@a74nh a74nh marked this pull request as ready for review June 13, 2025 14:13
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a74nh commented Jun 13, 2025

@dotnet/arm64-contrib @kunalspathak

@@ -702,9 +702,25 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_Sve_AndNot:
// Emit an unpredicated AND (to avoid the RMW constraints), then a predicated NOT
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Is that correct?

What happens for following code where inputs to AndNot are not masks, but vectors?

vector1 = Sve.Add() 
vector2 = Sve.Add() 
Sve.ConditionalSelect(mask, Sve.AndNot(vector1, vector2), op2)

I am hoping to see something like this:

and z4, p3/M, vector1, vector2
not result, p3/M, z4

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What happens for following code where inputs to AndNot are not masks, but vectors?

    static Vector<short> AndNot(Vector<short> v1, Vector<short> v2, Vector<short> v3, Vector<short> v4)
    {
        return Sve.ConditionalSelect(v1, Sve.AndNot(v2, v3), v4);
    }
IN0001: 000008      ptrue   p0.h
IN0002: 00000C      cmpne   p0.h, p0/z, z0.h, #0
IN0003: 000010      ptrue   p1.h
IN0004: 000014      and     z0.h, z1.h, z2.h
IN0005: 000018      not     z0.h, p1/m, z0.h
IN0006: 00001C      sel     z0.h, p0, z0.h, z3.h
    static Vector<short> AndNot(Vector<short> v1, Vector<short> v2, Vector<short> v3)
    {
        return Sve.ConditionalSelect(v1, Sve.AndNot(v2, v3), Vector<short>.Zero);
    }
IN0001: 000008      ptrue   p0.h
IN0002: 00000C      cmpne   p0.h, p0/z, z0.h, #0
IN0003: 000010      movi    v0.4s, #0
IN0004: 000014      and     z0.h, z1.h, z2.h
IN0005: 000018      not     z0.h, p0/m, z0.h

And I think that second one is incorrect - the false lanes will be the result of and(vec1,vec2)

It would be correct if using the predicated and. I just need to handle the RMW.

However - depending on the result of #115566 (comment) we may want to pause this PR.

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I don't think even first version is correct. Ideally, z0 or the destination of AndNot should have all the inactive lanes untouched, but from what we are getting, we will have the result of And operation in inactive lanes of destination.

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Arm64 SVE: Implement missing predicate methods
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