FiniteStateMachine upgrades

[mkorbel1]

Description & Motivation

This PR has a handful of upgrades to FiniteStateMachines so that it is easier to construct and generate readable FSM code.

• Add labels in generated verilog for FSMs (the final version of this should use SystemVerilog block labels #585)
• Add a way to set up defaults across all states (namely via setupActions), addressing "Default" values for FiniteStateMachines #509
• Perhaps: addressing Specifying the Sequential vs. Combinational driving of logic in FiniteStateMachine #313, still thinking about how/if to do it here or as a separate component/abstraction

Related Issue(s)

Fix #509

Testing

TODO

Existing tests cover much, but need to add more for new features

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No, it should not be

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

TODO

Yes, we should update examples