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Fix in erroneous implementation of _mm256_bsrli_epi128 #1823

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Merged
merged 9 commits into from
Jun 17, 2025
Merged

Fix in erroneous implementation of _mm256_bsrli_epi128 #1823

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b7f345e
Fix in erroneous implementation of _mm256_bsrli_epi128
satiscugcat Jun 3, 2025
21877dc
Removal of redundant mod operation in _mm256_alignr_epi8
satiscugcat Jun 3, 2025
fa67737
Fixing mistake in previous commit
satiscugcat Jun 3, 2025
311a99c
Changed the implementation of bsrli to match bslli in avx2 intrinsics
satiscugcat Jun 4, 2025
08e8140
Changed implementation of bsrli in avx512.rs to match that of bslli, …
satiscugcat Jun 4, 2025
e8cca99
Changed implementation of _mm{256,512}_alignr_epi8 to match that of _…
satiscugcat Jun 13, 2025
6c6b7e0
Moved const fn outside unsafe block
satiscugcat Jun 13, 2025
d8fd2db
Ran cargo fmt, removed unexpected character
satiscugcat Jun 13, 2025
4e6ec8d
Test
satiscugcat Jun 13, 2025
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4 changes: 2 additions & 2 deletions crates/core_arch/src/x86/avx2.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -191,7 +191,7 @@ pub fn _mm256_alignr_epi8<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
return transmute(a);
}

let r: i8x32 = match IMM8 % 16 {
let r: i8x32 = match IMM8 {
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@bjorn3 bjorn3 Jun 3, 2025 •
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You have to also add a value to the default arm. It is currently unreachable_unchecked(), which makes IMM8 values > 15 UB.
Edit: Maybe you should change the IMM8 == 16 if above to be IMM8 >= 16? Also there is handling for IMM8 > 16 above already: (_mm256_setzero_si256(), a) which would become unreachable in that case.

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Oh right, I was mistaken. I think specifically values between 17-31 (inclusive) are UB without the %, which makes it not redundant. My mistake!

0 => simd_shuffle!(
b,
a,
Expand Down Expand Up @@ -2964,7 +2964,7 @@ pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
unsafe {
let a = a.as_i8x32();
let zero = i8x32::ZERO;
let r: i8x32 = match IMM8 % 16 {
let r: i8x32 = match IMM8 {
0 => simd_shuffle!(
a,
zero,
Expand Down
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