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soc: intel_s1000: linker section size updates #11268

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sathishkuttan opened this issue Nov 9, 2018 · 0 comments
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soc: intel_s1000: linker section size updates #11268

sathishkuttan opened this issue Nov 9, 2018 · 0 comments
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bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug

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Currently, the sizes of text, data and bss sections are define separately (soc/xtensa/intel_s1000/memory.h)
The linker script (soc/xtensa/intel_s1000/linker.ld) uses these definitions for appropriately sizing the corresponding sections.
Depending on the application, the code/data sizes vary and this often results in updating the section size definitions in soc/xtensa/intel_s1000/memory.h
Since all these sections are mapped to the same physical memory block, it would be more flexible for application developers if the individual section limits are removed and there is only one limit defined for the sum of text, data and bss sections.

@nashif nashif added the bug The issue is a bug, or the PR is fixing a bug label Nov 13, 2018
@galak galak added the priority: low Low impact/importance bug label Nov 20, 2018
@nashif nashif removed their assignment Nov 20, 2018
rgundi added a commit to rgundi/zephyr that referenced this issue Nov 21, 2018
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.

Fixes zephyrproject-rtos#11268.

Signed-off-by: Rajavardhan Gundi <[email protected]>
nashif pushed a commit that referenced this issue Dec 11, 2018
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.

Fixes #11268.

Signed-off-by: Rajavardhan Gundi <[email protected]>
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