STM32 SPI/I2S: LSB bit corrupted for the received data

[avisconti]

On ArgonKey board I have experimented a bug in I2S which at the end turned out to be a known bug (id-bug: SPI-031111). Basically, when the APB clock is fast and the SPI/I2S GPIOs are configured slow, the Least Significant Bit of SPI/I2S data can be corrupted. This issue impacts the following SoCs:
STM32F1, STM32L0, STM32L1, STM32F3x (some 64K and 256K variants), STM32F2, STM32F4, STM32F0x (some 64K and 32 K variant)).

I was able to solve this issue reducing APB clock to half speed and putting the I2S gpios to high_speed.
Concerning the gpio speed setting I would like to discuss with @erwango how to solve this properly. We can set for each family the SPI/I2S gpios to high_speed, but maybe fast_speed is enough depending whether the SoC vdd is 1V8 or 3V3 (1V8 requires a faster gpio response). So, I opened this Issue for a proper discussion.

Other possibility:
Instead of adding a fixed speed in each pinmux include file (like pinmux_stm32f4.h) we may want to keep it parametric and add a proper speed value in the pinmux.c of the BSP.

[avisconti]

I know that @mariotesi found the (maybe) same issue on SPI on Nucleo F411 with zephyr. Let's fix it properly.

[avisconti]

For ArgonKey board I included the fix to this issue in the PR #9183.

Two things has been done:
A. APB2 clock has been slowed down to 42MHz.
B. The SPI/I2S clock gpio speed has been set to very_high_speed.

[avisconti]

I'm closing now this issue.