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Multiple tests are failing on sam_e70_xplained once the cache is enabled #9689

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spoorthik opened this issue Aug 28, 2018 · 7 comments
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bug The issue is a bug, or the PR is fixing a bug priority: high High impact/importance bug

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@spoorthik
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Due to commit c090776 multiple tests are failing on sam_e70_xplained.

@spoorthik
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Refer: #9684, #9683, #9682, #9680, #9677 for execution logs.

@tgorochowik
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That probably won't be very helpful, but if the original MPU/cache patches from #8185 are applied to the zephyr-v1.12.0 tag - the tests pass (and the cache works) (I remembered it to work and I just verified that).

So probably one of the recent MPU changes is causing all of this, not enabling the caches itself (but of course enabling them does trigger this bug).

@nashif nashif added bug The issue is a bug, or the PR is fixing a bug priority: high High impact/importance bug labels Aug 28, 2018
@nashif
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nashif commented Aug 28, 2018

merged now

@nashif nashif closed this as completed Aug 28, 2018
@aurel32
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aurel32 commented Nov 2, 2018

I have tried to re-enable the caches on the current git code, and I am not able to reproduce all those issues. @spoorthik, can you try to re-apply the patch enabling the caches to check it is also fixed on your side?

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aurel32 commented Nov 2, 2018

I forgot to say I do reproduce the issue with the commit just before the revert.

@spoorthik
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spoorthik commented Nov 3, 2018

@aurel32: I do reproduce the issue when I enable the caches on latest master and I don't if I disable.

Let me tell you what I did, please confirm if that is what are you expecting.

I am running the test at tests/mem_protect/mem_protect on latest commit: 8ded3fb

I don't see any issue now. - log attached.
mem_protect_tests_disabled_cache.txt

Now, I enable the cache:

diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c
index 86ed0d1..97f37bf 100644
--- a/soc/arm/atmel_sam/same70/soc.c
+++ b/soc/arm/atmel_sam/same70/soc.c

@@ -227,6 +227,12 @@ static int atmel_same70_init(struct device *arg)

        key = irq_lock();

+       SCB_EnableICache();
+
+       if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
+               SCB_EnableDCache();
+       }
+
        /* Clear all faults */
        _ClearFaults();

I can reproduce the issue. Log attached.
mem_protect_tests_enabled_cache.txt

@aurel32
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aurel32 commented Nov 3, 2018

@spoorthik, thanks for the test. I ran exactly the same thing, but I don't have the issue. I believe you are still interested to the cache enabled by default on the SAM E70 platform. I have therefore just opened the issue #11069 to discuss that, that is probably better than here.

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