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Merged
merged 3 commits into from
Nov 17, 2018
Merged

samples: net: lwm2m_client: build break fixes for k64F and pca10056 #11448

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2c4d9c7
samples: net: lwm2m_client: add "ok" and baud rate to k64f overlay
mike-scott Nov 16, 2018
5ab5591
dts-binding: modem: wnc-14a2a: remove base_label to fix build errors
mike-scott Nov 16, 2018
7b9adeb
samples: net: lwm2m_client: expand sanity testing
mike-scott Nov 16, 2018
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2 changes: 0 additions & 2 deletions dts/bindings/modem/wnc,m14a2a.yaml
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Expand Up @@ -50,6 +50,4 @@ properties:
category: optional
description: UART RTS pin if no HW flow control (set to always enabled)
generation: define, use-prop-name

base_label: WNCM14A2A
...
46 changes: 32 additions & 14 deletions samples/net/lwm2m_client/dts_fixup.h
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Expand Up @@ -5,19 +5,37 @@
*/

#ifdef CONFIG_BOARD_FRDM_K64F
#define DT_WNCM14A2A_UART_DRV_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_BUS_NAME
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_POWER_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_RESET_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN
#ifdef DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#define DT_WNCM14A2A_UART_DRV_NAME DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_BUS_NAME
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_POWER_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_RESET_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN
#ifdef DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NXP_KINETIS_UART_4006C000_WNC_M14A2A_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#endif
#endif

#if defined(CONFIG_BOARD_NRF52840_PCA10056) || defined(CONFIG_BOARD_NRF52840_MDK)
#define DT_WNCM14A2A_UART_DRV_NAME DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_BUS_NAME
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_POWER_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_RESET_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN
#ifdef DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NORDIC_NRF_UARTE_40028000_WNC_M14A2A_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#endif
#endif
3 changes: 3 additions & 0 deletions samples/net/lwm2m_client/frdm_k64f.overlay
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Expand Up @@ -4,6 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
&uart2 {
current-speed = <115200>;
status = "ok";

wncm14a2a {
compatible = "wnc,m14a2a";
label = "wncm14a2a";
Expand Down
19 changes: 18 additions & 1 deletion samples/net/lwm2m_client/sample.yaml
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Expand Up @@ -4,5 +4,22 @@ sample:
tests:
test:
harness: net
platform_whitelist: qemu_x86
depends_on: netif
platform_whitelist: qemu_x86 frdm_k64f
tags: net lwm2m
test_dtls:
harness: net
depends_on: netif
extra_args: OVERLAY_CONFIG=overlay-dtls.conf
platform_whitelist: qemu_x86 frdm_k64f
tags: net lwm2m
test_bt:
harness: net
extra_args: OVERLAY_CONFIG=overlay-bt.conf
platform_whitelist: nrf52_pca10040 nrf52840_pca10056 disco_l475_iot1
tags: net lwm2m
test_modem:
harness: net
extra_args: OVERLAY_CONFIG=overlay-wncm14a2a.conf
platform_whitelist: frdm_k64f nrf52840_pca10056
tags: net lwm2m
16 changes: 0 additions & 16 deletions soc/arm/nordic_nrf/nrf52/dts_fixup.h
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Expand Up @@ -148,20 +148,4 @@
#define DT_CC310_IRQ_PRI DT_ARM_CRYPTOCELL_310_5002B000_IRQ_0_PRIORITY
#endif

#define DT_WNCM14A2A_UART_DRV_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_BUS_NAME
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_POWER_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_RESET_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN
#ifdef DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER
#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN
#endif

/* End of SoC Level DTS fixup file */