boards: renesas: Add support Renesas ek_ra8p1 board

boards/renesas/ek_ra8p1/CMakeLists.txt

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources_ifdef(CONFIG_MEMC
+  SECTIONS sdram.ld)

boards/renesas/ek_ra8p1/Kconfig.defconfig

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EK_RA8P1
+
+if DISPLAY
+
+if SHIELD_RTKLCDPAR1S00001BE
+
+config MEMC
+	default y
+
+config RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION
+	default ".sdram"
+	depends on RENESAS_RA_GLCDC
+
+endif # SHIELD_RTKLCDPAR1S00001BE
+
+endif # DISPLAY
+
+if LVGL
+
+config LV_Z_VDB_CUSTOM_SECTION
+	default y
+
+endif # LVGL
+
+if DISK_DRIVER_SDMMC
+
+config SD_CMD_TIMEOUT
+	default 1000
+
+endif # DISK_DRIVER_SDMMC
+
+endif # BOARD_EK_RA8P1

boards/renesas/ek_ra8p1/Kconfig.ek_ra8p1

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA8P1
+	select SOC_R7KA8P1KFLCAC_CM85 if BOARD_EK_RA8P1_R7KA8P1KFLCAC_CM85
+	select SOC_R7KA8P1KFLCAC_CM33 if BOARD_EK_RA8P1_R7KA8P1KFLCAC_CM33

boards/renesas/ek_ra8p1/board.cmake

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_R7KA8P1KFLCAC_CM85)
+ board_runner_args(jlink "--device=R7KA8P1KF_CPU0" "--reset-after-load")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/renesas/ek_ra8p1/board.yml

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+board:
+  name: ek_ra8p1
+  full_name: RA8P1 Evaluation Kit
+  vendor: renesas
+  socs:
+  - name: r7ka8p1kflcac

boards/renesas/ek_ra8p1/doc/index.rst

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+.. zephyr:board:: ek_ra8p1
+
+Overview
+********
+
+The EK-RA8P1 is an Evaluation Kit for Renesas RA8P1 MCU Group which integrates multiple series of software-compatible
+Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient
+platform-based product development.
+
+The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm®
+Cortex®-M33 core running up to 250 MHz with the following features:
+
+- Up to 1 MB MRAM
+- 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM)
+- Arm® Ethos™-U55 NPU
+- Octal Serial Peripheral Interface (OSPI)
+- Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface
+- Graphics LCD Controller (GLCDC)
+- 2D Drawing Engine (DRW)
+- MIPI DSI/CSI interface
+- Analog peripherals
+- Security and safety features
+
+**MCU Native Pin Access**
+
+- 1GHz Arm Cortex-M85 and 250MHz Arm Cortex-CM33 based RA8P1 MCU in 289 pins, BGA package
+- Native pin access through 2 x 20-pin, and 2 x 40-pin headers (no populated)
+- Camera Expansion connector (present on the underside of the EK-RA8P1 board)
+- 2-Lane MIPI Display connector (present on the underside of the EK-RA8P1 board)
+- Parallel graphics display interface connector
+- MCU current measurement points for precision current consumption measurement
+- Multiple clock sources - RA8P1 MCU oscillator and sub-clock oscillator crystals,
+  providing precision 24.000MHz and 32,768 Hz refeence clocks.
+  Additional low precision clocks are available internal to the RA8P1 MCU
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (USB-C connector)
+- Four 5V input sources
+
+  - USB (Debug, Full Speed, High Speed)
+  - External power supply (using surface mount clamp test points and power input vias)
+
+- Three Debug modes
+
+  - Debug on-board (SWD and JTAG)
+  - Debug in (ETM, SWD, SWO and JTAG)
+  - Debug out (SWD, SWO, and JTAG)
+
+- User LEDs and buttons
+
+  - Three User LEDs (red, blue, green)
+  - Power LED (white) indicating availability of regulated power
+  - Debug LED (yellow) indicating the debug connection
+  - Ethernet LEDs (amber, yellow, green)
+  - Two User buttons
+  - One Reset button
+
+- Five most popular ecosystems expansions
+
+  - Two Seeed Grove system (I2C/I3C/Analog) connectors (not populated)
+  - One SparkFun Qwiic connector (not populated)
+  - Two Digilent Pmod (SPI, UART and I2C) connectors
+  - Arduino (Uno R3) connector
+  - MikroElektronika mikroBUS connector (not populated)
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- Ethernet (RJ45 RGMII interface)
+- USB High Speed Host and Device (USB-C connector)
+- 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8P1 board)
+
+Hardware
+********
+
+Detailed hardware features can be found at:
+
+- RA8P1 MCU: `RA Family 32-bit MCUs with Arm Cortex-M Core Website`_
+- EK-RA8P1 board: `Renesas RA Microcontroller Kits Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   - Other hardware features are currently not supported by the port.
+
+Programming and Debugging
+*************************
+
+Applications for the ``ek_ra8p1`` board configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application on cm85 core.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ek_ra8p1/r7ka8p1kflcac/cm85
+   :goals: flash
+
+Open a serial terminal, reset the board (press the S3 button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx *****
+   Hello World! ek_ra8p1/r7ka8p1kflcac/cm85
+
+Flashing
+========
+
+Program can be flashed to EK-RA8P1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+1. Connect to J-Link OB via USB port to host PC
+
+2. Make sure J-Link OB jumper is in default configuration as describe in `Renesas RA Microcontroller Kits Website`_
+
+3. Execute west command
+
+	.. code-block:: console
+
+		west flash -r jlink
+
+References
+**********
+- `Renesas RA Microcontroller Kits Website`_
+- `RA Family 32-bit MCUs with Arm Cortex-M Core Website`_
+
+.. _Renesas RA Microcontroller Kits Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra-kits
+
+.. _RA Family 32-bit MCUs with Arm Cortex-M Core Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus

boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi

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+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci8_default: sci8_default {
+		group1 {
+			/* tx */
+			psels = <RA_PSEL(RA_PSEL_SCI_8, 13, 2)>;
+			drive-strength = "medium";
+		};
+
+		group2 {
+			/* rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_8, 13, 3)>;
+		};
+	};
+
+	sci1_default: sci1_default {
+		group1 {
+			/* SDA SCL */
+			psels = <RA_PSEL(RA_PSEL_SCI_1, 4, 0)>,
+				<RA_PSEL(RA_PSEL_SCI_1, 4, 1)>;
+			drive-strength = "medium";
+			drive-open-drain;
+		};
+	};
+
+	spi1_default: spi1_default {
+		group1 {
+			/* MISO MOSI RSPCK SSL */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 0)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 1)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 2)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 3)>;
+		};
+	};
+
+	pwm1_default: pwm1_default {
+		group1 {
+			/* GTIOC1A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 5)>;
+		};
+
+		group2 {
+			/* GTIOC1B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 4)>;
+		};
+	};
+
+	iic1_default: iic1_default {
+		group1 {
+			/* SCL1 SDA1*/
+			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
+				<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
+			drive-strength = "medium";
+		};
+	};
+
+	canfd0_default: canfd0_default {
+		group1 {
+			/* CRX0 CTX0 */
+			psels = <RA_PSEL(RA_PSEL_CANFD, 2, 2)>,
+				<RA_PSEL(RA_PSEL_CANFD, 2, 3)>;
+			drive-strength = "high";
+		};
+	};
+
+	sdram_default: sdram_default {
+		group1 {
+		    /* SDRAM_DQM1 */
+		    psels = <RA_PSEL(RA_PSEL_BUS, 10, 5)>,
+		    /* SDRAM_CKE */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 6)>,
+		    /* SDRAM_WE */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 8)>,
+		    /* SDRAM_CS */
+		    <RA_PSEL(RA_PSEL_BUS, 8, 13)>,
+		    /* SDRAM_A0 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 3)>,
+		    /* SDRAM_A1 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 2)>,
+		    /* SDRAM_A2 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 1)>,
+		    /* SDRAM_A3 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 0)>,
+		    /* SDRAM_A4 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 3)>,
+		    /* SDRAM_A5 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 4)>,
+		    /* SDRAM_A6 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 5)>,
+		    /* SDRAM_A7 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 6)>,
+		    /* SDRAM_A8 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 7)>,
+		    /* SDRAM_A9 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 8)>,
+		    /* SDRAM_A10 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 9)>,
+		    /* SDRAM_A11 */
+		    <RA_PSEL(RA_PSEL_BUS, 5, 10)>,
+		    /* SDRAM_A12 */
+		    <RA_PSEL(RA_PSEL_BUS, 6, 8)>,
+		    /* SDRAM_D0 */
+		    <RA_PSEL(RA_PSEL_BUS, 3, 2)>,
+		    /* SDRAM_D1 */
+		    <RA_PSEL(RA_PSEL_BUS, 3, 1)>,
+		    /* SDRAM_D2 */
+		    <RA_PSEL(RA_PSEL_BUS, 3, 0)>,
+		    /* SDRAM_D3 */
+		    <RA_PSEL(RA_PSEL_BUS, 1, 12)>,
+		    /* SDRAM_D4 */
+		    <RA_PSEL(RA_PSEL_BUS, 1, 13)>,
+		    /* SDRAM_D5 */
+		    <RA_PSEL(RA_PSEL_BUS, 1, 14)>,
+		    /* SDRAM_D6 */
+		    <RA_PSEL(RA_PSEL_BUS, 1, 15)>,
+		    /* SDRAM_D8 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 11)>,
+		    /* SDRAM_D9 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 12)>,
+		    /* SDRAM_D10 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 13)>,
+		    /* SDRAM_D11 */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 14)>,
+		    /* SDRAM_D12 */
+		    <RA_PSEL(RA_PSEL_BUS, 6, 10)>,
+		    /* SDRAM_D13 */
+		    <RA_PSEL(RA_PSEL_BUS, 6, 11)>,
+		    /* SDRAM_D14 */
+		    <RA_PSEL(RA_PSEL_BUS, 6, 12)>,
+		    /* SDRAM_BA0 */
+		    <RA_PSEL(RA_PSEL_BUS, 13, 0)>,
+		    /* SDRAM_BA1 */
+		    <RA_PSEL(RA_PSEL_BUS, 12, 15)>,
+		    /* SDRAM_RAS */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 10)>,
+		    /* SDRAM_CAS */
+		    <RA_PSEL(RA_PSEL_BUS, 10, 9)>;
+		};
+
+		group2 {
+		    /* SDRAM_SDCLK */
+		    psels = <RA_PSEL(RA_PSEL_BUS, 10, 15)>;
+		    drive-strength = "highspeed-high";
+		};
+
+		group3 {
+		    /* SDRAM_D7 */
+		    psels = <RA_PSEL(RA_PSEL_BUS, 6, 9)>,
+		    /* SDRAM_D15 */
+		    <RA_PSEL(RA_PSEL_BUS, 6, 13)>,
+		    /* SDRAM_DQM0 */
+		    <RA_PSEL(RA_PSEL_BUS, 6, 14)>;
+		};
+	};
+};